M50FLW040A View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040A

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

Summary description

M50FLW040A, M50FLW040B

Figure 1.

Logic diagram (FWH/LPC interface)

VCC VPP

4

ID0-ID31

5

GPI0-GPI4

4

FWH0/LAD0

FWH3/LAD3

WP

FWH4/LFRAME M50FLW040A

TBL

M50FLW040B

CLK

IC

RP

INIT

VSS

AI08417B

1. ID3 is Reserved for Future Use (RFU) in LPC mode.

Table 1. Signal names (FWH/LPC Interface)

FWH0/LAD0-FWH3/LAD3

Input/Output Communications

FWH4/LFRAME

Input Communication Frame

ID0-ID3

Identification Inputs

GPI0-GPI4

General Purpose Inputs

IC

Interface Configuration

RP

Interface Reset

INIT

CPU Reset

CLK

Clock

TBL

Top Block Lock

WP

Write Protect

RFU

Reserved for Future Use. Leave disconnected

VCC

Supply Voltage

VPP

Optional Supply Voltage for Fast Program and Erase Operations

VSS

Ground

NC

Not Connected Internally

8/64

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