LC75853NW View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC75853NW

1/3 Duty LCD Display Drivers with Key Input Function

SANYO -> Panasonic 

LC75853NE, 75853NW

Voltage Detection Type Reset Circuit (VDET)

This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e.,

when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0 V, typical.

To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power

supply voltage VDD rise time when power is first applied and the power supply voltage VDD fall time when the voltage

drops are both at least 1 ms. (See Figure 3.)

System Reset

1. Reset method

If at least 1 ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied

by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage

VDD fall time when power drops, a system reset will be applied in the same manner by the VDET output signal when

the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (the display data D1

to D126 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last

direction data, after all the direction data has been transferred. (See Figure 3.)

Internal data

Display and control data transfer

Undefined

System reset period

Defined

Power supply voltage VDD rise time: t1 ≥ 1 ms

Power supply voltage VDD fall time: t2 ≥ 1 ms

Figure 3

2. LC75853NE/NW internal block states during the reset period

• CLOCK GENERATOR

Reset is applied and the base clock is stopped. However the OSC pin state (normal or sleep mode) is determined

after the S0 and S1 control data bits are transferred.

• COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.

• KEY SCAN

Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.

• KEY BUFFER

Reset is applied and all the key data is set to low.

• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

Since serial data transfer is possible, these circuits are not reset.

No. 4967-16/24

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