LC75863E View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC75863E Datasheet PDF : 24 Pages
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LC75863E, 75863W
3. Output pin states during the reset period
Output pin
S1/P1 to S4/P4
S5 to S23
COM1 to COM3
KS1/S24, KS2/S25
KS3 to KS5
KS6
DO
State during reset
L *5
L
L
L *5
X *6
H
H *7
X: don’t care
Note: *5.These output pins are forcibly set to the segment output function and held low.
*6.When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*7.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Sample Application Circuit 1
1/2 bias (for use with normal panels)
+5 V
+5.5 V
C ≥ 0.047 µF
From the
controller
To the controller
To the controller
power supply
*9
VDD
OSC
*8
VSS
TEST
VLCD
VLCD1
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
VLCD2
C
S S S23
22
CE
54
CL
//
DI K K K K K
DO
IIIII
54321
KKKKKK
SSSSSS
654321
(general-purpose
(P1) output ports)
(P2)
Used with the
(P3)
backlight controller
(P4)
or other circuit.
(S24)
(S25)
Key matrix
(up to 30 keys)
Note: *8.
*9.
Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7135-18/24
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