AS7C256 View Datasheet(PDF) - Alliance Semiconductor

Part Name

Description

Manufacturer

AS7C256

High Performance 32K×8 CMOS SRAM

Alliance Semiconductor 

AS7C256

AS7C256L

READ CYCLE 3, 9

Parameter

Read Cycle Time

Address Access Time

Chip Enable (CE) Access Time

Output Enable (OE) Access Time

Output Hold from Address Change

CE LOW to Output in Low Z

CE HIGH to Output in High Z

OE LOW to Output in Low Z

OE HIGH to Output in High Z

Power Up Time

Power Down Time

(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

-10

-12

-15

-20

-25

-35

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes

tRC

tAA

tACE

tOE

tOH

tCLZ

tCHZ

tOLZ

tOHZ

tPU

tPD

10 – 12 – 15 – 20 – 25 – 35 – ns

– 10 – 12 – 15 – 20 – 25 – 35 ns 3

– 10 – 12 – 15 – 20 – 25 – 35 ns 3

– 3 – 3 – 4 – 5 – 6 – 8 ns

2 – 3 – 3 – 3 – 3 – 3 – ns 5

3 – 3 – 3 – 3 – 3 – 3 – ns 4, 5

– 3 – 3 – 4 – 5 – 6 – 8 ns 4, 5

0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5

– 3 – 3 – 4 – 5 – 6 – 8 ns 4, 5

0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5

– 10 – 12 – 15 – 20 – 25 – 35 ns 4, 5

TIMING WAVEFORM OF READ CYCLE 13, 6, 7, 9

(Address Controlled)

Address

Dout

tRC

tAA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tOH

Data Valid

TIMING WAVEFORM OF READ CYCLE 23, 6, 8, 9

CE

OEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

Dout

tACE

tCLZ

tRC1

tOE

tOLZ

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

Supply

Current

tPU

50%

(CE Controlled)

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tOHZ

tCHZ

Data Valid

tPD

50%

ICC

ISB

AS7C256-04

4

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