MP7680 View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
MP7680 Datasheet PDF : 12 Pages
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MP7680
Transferring Data to the DAC Latches
Once one or all of the input latches have been loaded, the
condition XFER = WR2= low transfers the content of ALL
the input latches in the DAC latches. The output of the
DAC latches (DA11-DA0) changes and the DAC current
(IOUT) will reach a new stable value within the settling time
tS (Figure 6. ).
Examples of DACs updating sequences:
1) Simultaneous updates of any number of DACs. The
system uses from one (two) to four (eight) cycles to
write from a 12 (8) bit bus into B1/B2 latches. One
transfer cycle updates the output of all DACs
(Figure 7. )
2) Individual DAC update. The condition WR2 = XFER =
low makes the DAC latches transparent. A writing to
the B1/B2 latches updates the DAC outputs (Figure 8. ).
3) Automatic transfer to DAC latches. An 8-bit bus can
update any DAC with two cycles by connecting WR1 =
WR2 and B1/B2= XFER. This is the correct individual
DAC update for 8-bit busses (Figure 9. ).
4) Transfer by a second device. A processor may load the
input latches while the final XFER pulse is left to an-
other device.
CS
A0, A1
DATA
WR1
XFER=WR2
IOUT1A, B, C, D
=0
Valid
=1
Valid
=2
Valid
=3
Valid
Figure 7. Simultaneous Updates of DACs
CS
A1, A0
DATA
WR1
WR2 = XFER
IOUT1B
IOUT1D
=1
Valid
=3
Valid
Figure 8. Individual DAC Update
Rev. 3.10
CS
A1, A0
=1
=2
B1/B2 and XFER
WR1 and WR2
IOUTB
IOUTC
Figure 9. Automatic Transfer to DAC Latches
10
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