L6245 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

L6245

5V HARD DISK DRIVE POWER COMBO

STMicroelectronics 

L6245

ELECTRICAL CHARACTERISTICS (Continued)

Step-up converter

Symbol

Parameter

VSU

Step-up Voltage

Microprocessor interface (Note 10)

Test Condition

Relative to VCC

Min.

7

Typ.

Max. Units

11

V

Symbol

VIH

VIL

VOH

VOL1

Parameter

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

VOL2

Low Level Output Voltage

IIN1

Input Leakage Current

IIN2

Input Leakage Current

Microprocessor interface timing

Test Condition

VCC = 5V, IOH = 400µA

–MCERR, –POR, –DTACK

IOL = 4mA

SYNT_ALL

IOL = 0.5mA

–RD, –WR, AS, –MC_CS,

SYSCLK, A [0:2]

D [0:7]

Min.

3

4.4

Typ.

Max.

0.8

0.4

Units

V

V

V

V

0.4

V

1

µA

10

µA

Trddh Read Data Hold

Trddt

–RD High to –DTACK high

Twrdt –WR High to –DTACK High

Power on reset

5

40

ns

40

ns

40

ns

VCCHL

VCCHL

TPLH

RT

VCC Good, HL

VCC Good, LH

Rise Time

Response Time

VCC falling

VCC rising

CLoad = 100pF

4.2

4.4

V

4.26

4.5

V

200

ns

50

µs

Notes:

1) The minimum voltage available from the brushless DC motor after power has been removed is 2.7V

2) The voltage available for actuator etraction shall be greater than 0.7V.

3) Sum of Ibias+(Vref/internal resistor + power leakage).

4) Minimum output voltage is set to Vref by a resistor network.

5) The VCM DAC shall be monotonic over its full range.

6) The coding of the digital input shall be 2’s complement.

7) The voltage available for solenoid operation shall be greater than 1.9V.

8) The Spin DAC shall be monotonic over its full range.

9) The coding of the digital input shall be uniplar (unsigned binary).

10) SYNTH_HALL, MC_ERR, DTACK and POR shall have open drain (collector) outputs and internal pull-up resistors. The minimum value of

these pull-up resistors shall be 20KΩ..

FUNCTIONAL DESCRIPTION

Inside the system is the sensorless Spindle driver

(Spin), the Voice Coil Motor driver (VCM), the

Head load/unload predrivers, power sequencing,

actuator over-velocity detection, actuator retrac-

tion and dynamic braking. The architecture of the

system is configured to interface directly to an 8

bit, parallel, microprocessor bus.

During the application of power to the system

(power-on), the output drivers are held in a disabled

state until the applied voltage reaches the Voltage

Good Threshold (VGT). During this period of time

the output drivers are disabled, the internal register

are set to predetermined states, and the Power On

Reset (POR) signal is held low. The POR signal is

held low from the time the applied voltage

reaches 0.7V and the VGT. The POR delay is

programmable changing the value of a capacitor.

The VCM driver is driven via a D/A and it can be

enabled through the VCM driver register. The

VCM driver has a gain capability too. This func-

tion is to be accomplished by switching the sense

resistor used such that the current sensing feed-

back in the VCM driver has more information and

therefore results in lower deadband, offset cur-

rent, and gain error. An actuator over velocity

sensing circuit is incorporated in the system,

which is accomplished by measuring BEMF volt-

age and comparing to a threshold.

9/15

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