MAX1710 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX1710

High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs

Maxim Integrated 

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, VBATT = 15V, VCC = VDD = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted.)

PARAMETER

CONDITIONS

MIN TYP

Overvoltage Trip Threshold

With respect to unloaded output voltage (MAX1710)

(MAX1711/MAX1712)

10.5 12.5

2.21 2.25

Overvoltage Fault Propagation

Delay

FB forced 2% above trip threshold

1.5

Output Undervoltage Protection With respect to unloaded output voltage (MAX1710)

Threshold

(MAX1711/MAX1712)

65

70

0.76 0.8

Output Undervoltage Protection

Time

From SHDN signal going high

10

Current-Limit Threshold

(Positive Direction, Fixed)

LX to PGND, ILIM tied to VCC

90

100

Current-Limit Threshold

(Positive Direction, Adjustable)

LX to PGND RLIM = 100kΩ

RLIM = 400kΩ

40

50

170

200

Current-Limit Threshold

(Negative Direction)

LX to PGND, TA = +25°C

-150 -120

Current-Limit Threshold

(Zero Crossing)

LX to PGND

3

PGOOD Propagation Delay

FB forced 2% below PGOOD trip threshold, falling edge

1.5

PGOOD Output Low Voltage

ISINK = 1mA

PGOOD Leakage Current

High state, forced to 5.5V

Thermal Shutdown Threshold Hysteresis = 10°C

150

VCC Undervoltage Lockout

Threshold

Rising edge, hysteresis = 20mV,

PWM disabled below this level

4.1

DH Gate-Driver On-Resistance BST-LX forced to 5V

DL Gate-Driver On-Resistance

(Pullup)

DL, high state

DL Gate-Driver On-Resistance

(Pulldown)

DL, low state

0.5

DH Gate-Driver Source/Sink

Current

DL Gate-Driver Sink Current

DL Gate-Driver Source Current

Dead Time

SKIP Input Current Logic

Threshold

DH forced to 2.5V, BST-LX forced to 5V

DL forced to 2.5V

DL forced to 2.5V

DL rising

DH rising

To enable no-fault mode, TA = +25°C

1

3

1

35

26

-1.5

PGOOD Trip Threshold

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

Logic Input Pullup Current

Measured at FB with respect to unloaded output voltage,

falling edge, hysteresis = 1%

-8

-5

D0–D4, SHDN, SKIP, OVP

D0–D4, SHDN, SKIP, OVP

SHDN, SKIP, OVP

D0–D4, each forced to GND

2.4

-1

3

5

MAX

14.5

2.29

75

0.84

30

UNIT

%

V

µs

%

V

ms

110

mV

60

mV

230

-80

mV

mV

µs

0.4

V

1

µA

°C

4.4

V

5

Ω

5

Ω

1.7

Ω

A

A

A

ns

-0.1

mA

-3

%

V

0.8

V

1

µA

10

µA

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