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MAX3670 View Datasheet(PDF) - Maxim Integrated

Part Name
Description
Manufacturer
MAX3670 Datasheet PDF : 12 Pages
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Low-Jitter 155MHz/622MHz
Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V ±10% or VCC = +5.0V ±10%, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless other-
wise noted.) (Note 5)
PARAMETER
PLL SPECIFICATIONS
PLL Jitter Transfer Bandwidth
Jitter Transfer Function
OP AMP SPECIFICATION
Unity-Gain Bandwidth
VCO INPUT SPECIFICATION
VCO Input Frequency
VCO Input Slew Rate
SYMBOL
CONDITIONS
BW
(Note 10)
FJITTER BW (Note 11)
fVCO
MIN TYP MAX UNITS
15
20,000 Hz
0.1
dB
7
MHz
622/155 670
0.5
MHz
V/ns
Note 1: Specifications at -40°C are guaranteed by design and characterization.
Note 2: Measured with PECL outputs unterminated.
Note 3: OPAMP specifications met with 10kΩ load to ground or 5kΩ load to VCC (POLAR = 0 and POLAR = VCC).
Note 4: PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 3 for gain settings.
Note 5: AC characteristics are guaranteed by design and characterization.
Note 6: Measured with 50% VCO input duty cycle.
Note 7: Random noise voltage at op amp output with 800kΩ resistor connected between VC and OPAMP-, PFD/CP gain (KPD) =
5µA/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input.
Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1 = 800kΩ, KPD = 5µA/UI, and
compare frequency 400 times greater than the higher-order pole frequency (see Design Procedure).
Note 9: PSR measured with a 100mVp-p sine wave on VCC in a frequency range from 100Hz to 2MHz. External resistors R1 matched
to within 1%, external capacitors C1 matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz.
Note 10: The PLL 3dB bandwidth is adjusted from 15Hz to 20kHz by changing external components R1 and C1, by selecting the inter-
nal programmable divider ratio and phase-detector gain. Measured with VCO gain of 220ppm/V and C1 limited to 2.2µF.
Note 11: Measured at BW = 20kHz. When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls
off at -20dB/decade.
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