Low-Jitter 155MHz/622MHz Clock Generator
Chip Topography
C2+
C2-
VCCD
THADJ
GND
CTH
NSEL1
NSEL2
GSEL
37 36 35 34 33 32 31 30 29 28
1
27
2
26
3
25
4
24
5
23
6
22
7
21
8
20
9
19
10 11 12 13 14 15 16 17 18
GND
VCOIN+
VCOIN-
VCCD
MOUT+ 0.076"
MOUT- (1.930mm)
VCCD
POUT+
POUT-
Chip Information
PROCESS: GST2
SUBSTRATE CONNECTED TO GND
DIE THICKNESS: 14 mils
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
0.080"
(2.032mm)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.