MAX3627 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX3627 Datasheet PDF : 11 Pages
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+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
Pin Description
PIN
1
2
3, 9, 24, 32
4
5
6, 12, 19
7
8
10
11
13
14
15
16
17
18
20
21
22
23
25
26
27
28
29
30
31
—
NAME
Q0
Q0
GND
Q1
Q1
VDDO_DIFF
Q2
Q2
Q3
Q3
Q4
Q4
FSELB
OE
Q5
Q5
Q6
Q6
VDDO_SE
Q7
VDD
PLL_BP
VDDA
FSELA
OSC_IN
X_IN
X_OUT
EP
FUNCTION
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Supply Ground
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Power Supply for Q0, Q1, Q2, Q3, Q4, Q5, and Q6 Clock Outputs. Connect to +3.3V.
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Three-State LVCMOS/LVTTL Input. Controls the Q1 to Q7 output divider. When connected to logic-
low, the output frequency is 125MHz. When connected to logic-high, the output frequency is
156.25MHz. When left open (high-Z), the output frequency is 312.5MHz. For the Q7 LVCMOS output,
the output specification is only valid up to 160MHz.
LVCMOS/LVTTL Input. Enable/disable control for the Q4, Q5, and Q6 outputs. The OE pin has an
internal 75k pullup resistor. When OE is connected to VDD or left open, Q4, Q5, and Q6 are enabled.
When OE is connected to GND, Q4, Q5, and Q6 are disabled to reduce power consumption. When
disabled, Q4, Q5, and Q6 are high impedance.
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
LVDS, Noninverting Clock Output
LVDS, Inverting Clock Output
Power Supply for Q7 Clock Output. Connect to +3.3V.
LVCMOS Clock Output
Core Power Supply. Connect to +3.3V.
Three-State LVCMOS/LVTTL Input (Active Low). When connected to logic-high, the PLL locks to the
crystal interface (25MHz typical at X_IN and X_OUT). When left open (high-Z), the PLL locks to the
OSC_IN input (25MHz typical). When connected to logic-low, the PLL is bypassed and the OSC_IN
input is selected. When bypass mode is selected, the VCO/PLL is disabled to save power and
eliminate intermodulation spurs.
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this
pin can be connected to VDD through a 10.5 resistor as shown in Figure 4.
Three-State LVCMOS/LVTTL Input. Controls the Q0 output divider. When connected to logic-low, the
output frequency is 125MHz. When connected to logic-high, the output frequency is 156.25MHz.
When left open (high-Z), the output frequency is 312.5MHz.
LVCMOS Input. Self-biased to allow AC- or DC-coupling. When PLL_BP is open, the OSC_IN input
frequency should be 25MHz. When the PLL is in bypass mode (PLL_BP = low), the OSC_IN input
frequency can be between 20MHz and 320MHz. When PLL_BP is high, the OSC_IN should be
disconnected.
Crystal Oscillator Input
Crystal Oscillator Output
Exposed Pad. Connect to GND for proper electrical and thermal performance.
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