MAX6846 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX6846

Low-Power, Adjustable Battery Monitors with Hysteresis and Integrated µP Reset

Maxim Integrated 

Low-Power, Adjustable Battery Monitors with

Hysteresis and Integrated µP Reset

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 1.6V to 5.5V, VCC = 1.2V to 5.5V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

LBO, LBOL, LBOH Output

Open-Drain Leakage Current

Output deasserted

500

nA

VCC Reset Threshold

VCC Reset Hysteresis

VCC to RESET Delay

VCC to RESET Timeout Period

MR Input Voltage

MR Minimum Pulse Width

MR Glitch Rejection

MR to RESET Delay

MR Reset Timeout Period

MR Pullup Resistance

MR Rising Debounce Period

RESET Output High

(Push-Pull)

RESET Output Low

RESET Output Leakage Current

(Open Drain)

VTH

tRD

tRP

VIL

VIH

tMPW

tMRP

tDEB

VOH

VOL

MAX68_ _ _ _ T

3.000 3.075 3.150

MAX68_ _ _ _ S

2.850 2.925 3.000

MAX68_ _ _ _ R

2.550 2.625 2.700

MAX68_ _ _ _ Z

2.250 2.313 2.375

V

MAX68_ _ _ _ Y

MAX68_ _ _ _ W

2.125 2.188 2.250

1.620 1.665 1.710

MAX68_ _ _ _ V

1.530 1.575 1.620

0.3

%

VCC falling at 10mV/µs from (VTH + 100mV)

to (VTH - 100mV)

50

µs

MAX68_ _ _ _ _ D3

MAX68_ _ _ _ _ D7

150 225 300

ms

1200 1800 2400

0.7 x VCC

0.3 x VCC

V

1

µs

100

ns

200

ns

MR to VCC

(Note 3)

150 225 300

ms

750 1500 2250

Ω

150 225 300

ms

VCC ≥ 1.53V, ISOURCE = 100µA, RESET

deasserted

0.8 x VCC

VCC ≥ 2.55V, ISOURCE = 500µA, RESET

deasserted

VCC ≥ 1.0V, ISINK = 50µA, RESET asserted

VCC ≥ 1.2V, ISINK = 100µA, RESET asserted

VCC ≥ 2.12V, ISINK = 1.2mA, RESET

asserted

0.8 x VCC

V

0.3

0.3

V

0.3

RESET deasserted

500

nA

Note 1: Production testing done at TA = +25°C; limits over temperature guaranteed by design only.

Note 2: The device is powered up by the highest voltage between VDD and VCC.

Note 3: MR input ignores falling input pulses, which occur within the MR debounce period (tDEB) after a valid MR reset assertion.

This prevents invalid reset assertion due to switch bounce.

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