MAX809 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
MAX809 Datasheet PDF : 12 Pages
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MAX809 Series, MAX810 Series
APPLICATIONS INFORMATION
VCC Transient Rejection
The MAX809 provides accurate VCC monitoring and reset
timing during power–up, power–down, and brownout/sag
conditions, and rejects negative–going transients (glitches)
on the power supply line. Figure 2 shows the maximum
transient duration vs. maximum negative excursion
(overdrive) for glitch rejection. Any combination of
duration and overdrive which lies under the curve will not
generate a reset signal. Combinations above the curve are
detected as a brownout or power–down. Typically, transient
that goes 100 mV below the reset threshold and lasts 5 µs or
less will not cause a reset pulse. Transient immunity can be
improved by adding a capacitor in close proximity to the VCC
pin of the MAX809.
VCC
VTH
Overdrive
Duration
120
100
80
60
VTH = 4.9 V
40
VTH = 1.6 V
20
0
10.0
60.0
110.0
160.0
RESET COMPARATOR OVERDRIVE (mV)
Figure 2. Maximum Transient Duration vs. Overdrive
for Glitch Rejection at 25°C
RESET Signal Integrity During Power–Down
The MAX809 RESET output is valid to VCC = 1.0 V.
Below this voltage the output becomes an “open circuit” and
does not sink current. This means CMOS logic inputs to the
µP will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
valid to VCC = 0 V, a pull–down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 3). This resistor value, though
not critical, should be chosen such that it does not
appreciably load RESET under normal operation (100 kW
will be suitable for most applications).
VCC
VCC
MAX809/810
RESET
RESET
GND
R1
100 k
Figure 3. Ensuring RESET Valid to VCC = 0 V
Processors With Bidirectional I/O Pins
Some µP’s (such as Motorola 68HC11) have
bi–directional reset pins. Depending on the current drive
capability of the processor pin, an indeterminate logic level
may result if there is a logic conflict. This can be avoided by
adding a 4.7 kW resistor in series with the output of the
MAX809 (Figure 4). If there are other components in the
system which require a reset signal, they should be buffered
so as not to load the reset line. If the other components are
required to follow the reset I/O of the µP, the buffer should
be connected as shown with the solid line.
VCC
VCC
MAX809/810
RESET
RESET
GND
4.7 k
BUFFER
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
VCC
mP
RESET
GND
Figure 4. Interfacing to Bidirectional Reset I/O
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