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MAX835(1996) View Datasheet(PDF) - Maxim Integrated

Part Name
Description
Manufacturer
MAX835
(Rev.:1996)
MaximIC
Maxim Integrated MaximIC
MAX835 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Micropower, Latching Voltage Monitors
in SOT23-5
_______________Detailed Description
The MAX834/MAX835 micropower voltage monitors con-
tain a 1.204V precision bandgap reference and a com-
parator with an output latch (Figure 1). The difference
between the two parts is the structure of the comparator
output driver. The MAX834 has an open-drain, N-channel
output driver that can be pulled up to a voltage higher
than VCC, but less than 11V. The MAX835’s output is
push/pull and can both source and sink current.
Programming the Trip Voltage (VTRIP)
Two external resistors set the trip voltage, VTRIP (Figure
2). VTRIP is the point at which the falling monitored volt-
age (typically VCC) causes OUT to go low. IN’s high
input impedance allows the use of large-value
resistors without compromising trip voltage accuracy. To
minimize current consumption, choose a value for R2
between 500kand 1M, then calculate R1 as follows:
R1 = R2 [(VTRIP / VTH) - 1]
where VTRIP is the desired trip voltage and VTH is the
threshold voltage (1.204V). The voltage at IN must be at
least 1V less than VCC.
Latched-Output Operation
The MAX834/MAX835 feature a level-sensitive latch
input (CLEAR), designed to eliminate the need for hys-
teresis in battery undervoltage-detection applications.
When the monitored voltage (VMON) is above the pro-
grammed trip voltage (VTRIP) (as when the system bat-
tery is recharged or a fresh battery is installed), pulse
CLEAR low-high-low for at least 1µs to reset the output
latch (OUT goes high). When VMON falls below VTRIP,
OUT goes low and remains low (even if VMON rises
above VTRIP), until CLEAR is pulsed high again with
VMON > VTRIP. Figure 3 shows the timing relationship
between VMON, OUT, and CLEAR.
> VTRIP
VMON
< VTRIP
VCC
CLEAR
0V
VCC
OUT
0V
Figure 3a. Timing Diagram
> 1µs
> 1µs
> 1µs
> VTRIP
VMON
< VTRIP
VCC
OUT
0V
Figure 3b. Timing Diagram, CLEAR = VCC
6 _______________________________________________________________________________________

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