MAX8566(2005) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX8566 Datasheet PDF : 21 Pages
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High-Efficiency, 10A, PWM
Internal-Switch Step-Down Regulator
The peak inductor current (IP-P) is:
IP−P
=
VIN − VOUT
fs × L
×
VOUT
VIN
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The low ESL of ceramic
capacitors makes ripple voltages negligible.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ILOAD. Before the controller
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time (see the Typical Operating Characteristics), the
controller responds by regulating the output voltage
back to its predetermined value. The controller
response time depends on the closed-loop bandwidth.
A higher bandwidth yields a faster response time, pre-
venting the output from deviating further from its regu-
lating value. See the Compensation Design section for
more details.
Input Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do
not pass through the input source but are instead
shunted through the input capacitor. High source
impedance requires high input capacitance. The input
capacitor must meet the ripple-current requirement
imposed by the switching currents. The RMS input rip-
ple current is given by:
( ) IRIPPLE = ILOAD ×
VOUT × VIN − VOUT
VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the out-
put filtering inductor, L, and the output filtering capaci-
tor, CO. The ESR of the output filtering capacitor
determines the zero. The double pole and zero fre-
quencies are given as follows:
fP1_LC = fP2_LC =
2π ×
1
L
×
CO
×
⎛
⎝⎜
RO + ESR
RO + RL
⎞
⎠⎟
fZ _ESR
=
2π
×
1
ESR
×
CO
where RL is equal to the sum of the output inductor’s
DCR and the internal switch resistance, RDSON. A typi-
cal value for RDSON is 8mΩ. RO is the output load
resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total
equivalent series resistance of the output filtering
capacitor. If there is more than one output capacitor of
the same type in parallel, the value of the ESR in the
above equation is equal to that of the ESR of a single
output capacitor divided by the total number of output
capacitors.
The high switching frequency range of the MAX8566
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer-function zero is high-
er than the unity-gain crossover frequency, fC, and the
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 90 degrees per decade. The error ampli-
fier must compensate for this gain drop and phase shift
to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use Type 3 compensation as shown in
Figure 4. Type 3 compensation possesses three poles
and two zeros with the first pole, fP1_EA, located at 0
frequency (DC). Locations of other poles and zeros of
the Type 3 compensation are given by:
fZ1_EA
=
2π
×
1
R1 ×
C1
fZ2 _ EA
=
2π
×
1
R3
×
C3
fP2 _ EA
=
2π
×
1
R1 ×
C2
fP3 _ EA
=
2π
×
1
R2
×
C3
The above equations are based on the assumptions
that C1>>C2, and R3>>R2, which are true in most
applications. Placement of these poles and zeros is
16 ______________________________________________________________________________________
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