MAX9321B View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX9321B Datasheet PDF : 7 Pages
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Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
Pin Description
PIN
NAME
FUNCTION
1
N.C. No Connection
2
D
Noninverting Differential Input. 80kΩ pullup to VCC, 60kΩ pulldown to VEE.
3
D
Inverting Differential Input. 50kΩ pullup to VCC and 100kΩ pulldown to VEE.
4
VBB
Reference Output Voltage. Connect to the inverting or noninverting input to provide a reference for single-
ended operation. When used, bypass with a 0.01µF ceramic capacitor to VCC; otherwise leave open.
5
VEE
Negative Supply Voltage
6
Q
Inverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
7
Q
Noninverting Output. Typically terminate with 50Ω resistor to VCC - 2V.
8
VCC
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Detailed Description
The MAX9321B low-skew differential receiver/driver is
designed for clock and data distribution. For interfacing
to differential PECL/LVPECL signals, this device oper-
ates over a +3.0V to +5.5V supply range, allowing high-
performance clock and data distribution in systems with
a nominal 3.3V or 5V supply. For differential ECL/
LVECL operation, this device operates from a -3.0V to
-5.5V supply.
Inputs
The differential input can be configured to accept a sin-
gle-ended input. This is accomplished by connecting
the on-chip reference voltage, VBB, to an input as a ref-
erence. For example, the differential input is converted
to a noninverting, single-ended input by connecting
VBB to D and connecting the single-ended input to D.
An inverting input is obtained by connecting VBB to D
and connecting the single-ended input to D.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBB reference
is not used, it can be left open. The VBB reference can
source or sink 0.5mA. Use VBB only for an input on the
same device as the VBB reference.
The maximum magnitude of the differential input from D
to D is 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 50kΩ pullup to VCC
and a 100kΩ pulldown to VEE. The noninverting input is
biased with an 80kΩ pullup to VCC and a 60kΩ pull-
down to VEE.
Specifications for the high and low voltage of the differ-
ential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the VCC supply. With VCC connected to a posi-
tive supply and VEE connected to GND, the output is
PECL/LVPECL. The output is ECL/LVECL when VCC is
connected to GND and VEE is connected to a negative
supply.
A single-ended input of at least VBB ±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the VOH and VOL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance. When using the VBB
reference output, bypass it with a 0.01µF ceramic
capacitor to VCC (if the VBB reference is not used, it
can be left open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9321B. Connect each signal of a differ-
ential input or output to a 50Ω characteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ω characteristic impedance through connectors and
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