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MAX9687CSE View Datasheet(PDF) - Maxim Integrated

Part Name
Description
Manufacturer
MAX9687CSE
MaximIC
Maxim Integrated MaximIC
MAX9687CSE Datasheet PDF : 4 Pages
1 2 3 4
Dual, Ultra-Fast ECL-Output Comparator
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Both poor layout
and larger source impedance will increase the mini-
mum slew-rate specification.
In many applications, the addition of regenerative feed-
back will assist the input signal through the linear
region, which will lower the minimum slew-rate require-
ment considerably. For example, with the addition of
positive feedback components Rf = 1kand
Cf = 10pF, the minimum slew-rate requirement can be
reduced by a factor of four.
____________________Timing Diagram
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions.
The top line of the diagram illustrates two latch-enable
(LE) pulses; each pulse is high for the compare func-
tion and low for the latch function. The first pulse
demonstrates the compare function in which part of the
input action takes place during the compare mode.
The second pulse demonstrates a compare-function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude,
comparator after
small-overdrive
time interval tpd.
pulse) switches
Outputs Q and
th–Qe–
are similar in timing. The input signal must occur at time
ts before the latch falling edge and, to be acquired,
must be maintained for time th after the edge. After th,
the output is no longer affected by the input status until
the latch is again strobed. A minimum latch pulse width
of tpw(E) is needed for the strobe operation, and the
output transitions occur after a time tpd(E).
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
LATCH
VIN
Q
COMPARE
ts
th
VOD
tpd
Definition of Terms
VOS Input Offset Voltage—The voltage required
between the input terminals to obtain 0V differ-
ential at the output.
VIN Input Voltage Pulse Amplitude
VOD Input Voltage Overdrive
tpd+ Input to Output High Delay—The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50% point
of an output low-to-high transition.
tpd- Input to Output Low Delay—The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50% point
of an output high-to-low transition.
tpd+(E) Latch-Enable to Output High Delay—The propa-
gation delay measured from the 50% point of the
latch-enable signal low-to-high transition to the
50% point of an output low-to-high transition.
tpd-(E)
Latch-Enable to Output Low Delay—The propa-
gation delay measured from the 50% point of the
latch-enable signal low-to-high transition to the
50% point of an output high-to-low transition.
tpw(E) Minimum Latch-Enable Pulse Width—The mini-
mum time the latch-enable signal must be high
to acquire and hold an input signal.
ts
Minimum Setup Time—The minimum time before
the negative transition of the latch-enable pulse
that an input signal must be present to be
acquired and held at the outputs.
th
Minimum Hold Time—The minimum time after
the negative transition of the latch-enable signal
that an input signal must remain unchanged to
be acquired and held at the outputs.
50%
tpw (E)
VOS
tpd (E)
50%
Q
50%
Figure 3. Timing Diagram
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
4 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1993 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.

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