MB1502 View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MB1502

SERIAL INPUT PLL FREQUENCY SYNTHESIZER

Fujitsu 

MB1502

FUNCTIONAL DESCRIPTIONS

SERIAL DATA INPUT

Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable

reference divider and 18-bit programmable divider, respectively.

Binary serial data is input to Data pin.

On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored

data is transferred into latch depending upon the control bit.

Control data “H” data is transferred into 15-bit latch.

Control data “L” data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER

Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is

shown below.

Control bit

LSB

Divide ratio of prescaler setting bit

MSB

CSSSSSSSSSSSSSSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 W

Divide ratio of programmable reference counter setting bit

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO

Divide S S S S S S S S S S S S S S

Ratio

R

14 13 12 11 10 9 8 7 6 5 4 3 2 1

8

00000000001000

9

00000000001001

•

••••••••••••••

16383

11111111111111

NOTES: Divide ratio less than 8 is prohibited.

Divide ratio: 8 to 16383

SW: This bit selects divide ratio of prescaler.

SW=H : 64

SW=L :128

S1 to S14: These bits select divide ratio of programmable reference divider.

C: Control bit (sets as high level).

Data is input from MSB side.

PROGRAMMABLE DIVIDER

Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.

Serial 19-bit data format is shown on following page.

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