MB89580B/580BW series
(Continued)
• PLL clock control
The internal PLL clock circuit allows the use of low-speed clocks which are advantageous to noise character-
istics.
(6 MHz externally-supplied clock→12 MHz internal system clock)
• Various timers
8-bit PWM timer (can be used as either 8-bit PWM timer × 2 channels or PPG timer × 1 channel)
Internal 21-bit timebase timer
• Internal USB transceiver circuit (Compatible with full and low speeds)
• USB function
Compliant to USB Protocol Revision 1.0
Support for both low and full speeds (selectable)
Allows four endpoints to be specified at maximum.
Types of transfer supported : control/interrupt/bulk/isochronous
Built-in DMAC (Maps the buffer for each endpoint on to the internal RAM to directly access the memory for
function’s send and receive data.)
• UART/serial interface
Built-in UART/SIO function (selectable by switching)
• External interrupt
External interrupt (level detection × 8 channels)
Eight inputs are independent of one another and can also be used for resetting from low-power consumption
mode (the L-level detection feature available) .
• Low power consumption (standby mode supported)
Stop mode (There is almost no current consumption since oscillation stops.)
Sleep mode (This mode stops the running CPU.)
• A maximum of 53 general-purpose I/O ports
General-purpose I/O ports (CMOS) : 34
General-purpose output ports (CMOS) : 8
General-purpose I/O ports (Nch open drain) : 3
General-purpose input ports (CMOS 3.3 V input-compatible) : 8
• Parallel ports
Also serve as eight of the general-purpose I/O ports (CMOS)
Interrupt function available
Allows asynchronous read and write by external signals
• Power supply
Supply voltage : 3.0 V to 5.5 V
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