MB91106PFV View Datasheet(PDF) - Fujitsu
Part Name
Description
Manufacturer
MB91106PFV Datasheet PDF : 116 Pages
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MB91106 Series
Pin no.
LQFP*1 QFP*2
23
26
Pin name
P84
WR0
24
27 WR1
P85
11
14 CS0
PA0
10
13 CS1
PA1
9
12 CS2
PA2
8
11 CS3
PA3
EOP1
7
10 CS4
PA4
6
9 CS5
PA5
5
8 CLK
PA6
*1: FPT-100P-M05
*2: FPT-100P-M06
Circuit
type
Function
E Can be configured as general purpose I/O port when WR0 is
not used.
Write strobe output pin for external bus
Relation between control signals and effective byte locations is
as follows:
E
16-bit
8-bit
Single chip
bus width bus width
mode
D31 to D24
WR0
WR0
(I/O port
enabled)
D23 to D16
WR1
(I/O port
enabled)
(I/O port
enabled)
Note: WR1 is Hi-Z during resetting.
Attach an external pull-up resister when using at 16-bit
bus width.
Can be configured as general purpose I/O port when WR1 is
not used.
E Chip select 0 output (“L” active)
Can be configured as general purpose I/O port when CS0 is
not used.
E Chip select 1 output (“L” active)
Can be configured as general purpose I/O port when CS1 is
not used.
E Chip select 2 output (“L” active)
Can be configured as a port when CS2 is not used.
E Chip select 3 output (“L” active)
Can be configured as a port when CS3 and EOP1 are not
used.
EOP output pin for DMAC (ch. 1)
This function is available when EOP output for DMAC is
enabled.
E Chip select 4 output (“L” active)
Can be configured as general purpose I/O port when CS4 is
not used.
E Chip select 5 output (“L” active)
Can be configured as general purpose I/O port when CS5 is
not used.
E System clock output
Outputs clock signal of external bus operating frequency.
Can be configured as general purpose I/O port when CLK is
not used.
(Continued)
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