MB91106PFV View Datasheet(PDF) - Fujitsu
Part Name
Description
Manufacturer
MB91106PFV Datasheet PDF : 116 Pages
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MB91106 Series
Pin no.
LQFP*1 QFP*2
96
99
Pin name
RAS0
PB0
97
100 CS0L
PB1
98
1 CS0H
PB2
99
2 DW0
PB3
100
3 RAS1
PB4
EOP2
1
4 CS1L
PB5
DREQ2
2
5 CS1H
PB6
DACK2
3
6 DW1
PB7
16 to 18 19 to 21 MD0 to MD2
92
95
91
94
14
17
12
15
*1: FPT-100P-M05
*2: FPT-100P-M06
8
X0
X1
RST
NMI
Circuit
type
Function
E RAS output for DRAM bank 0
Can be configured as general purpose I/O port when RAS0 is
not used.
E CASL output for DRAM bank 0
Can be configured as general purpose I/O port when CS0L is
not used.
E CASH output for DRAM bank 0
Can be configured as general purpose I/O port when CS0H is
not used.
E WE output for DRAM bank 0 (“L” active)
Can be configured as general purpose I/O port when DW0 is
not used.
E RAS output for DRAM bank 1
Can be configured as general purpose I/O port when RAS1
and EOP2 are not used.
DMAC EOP output (ch. 2)
This function is available when DMAC EOP output is enabled.
E CASL output for DRAM bank 1
Can be configured as general purpose I/O port when CS1L
and DREQ are not used.
External transfer request input pin for DMA
This pin is used for input when external trigger is selected to
cause DMAC operation, and it is necessary to disable output
for other functions from this pin unless such output is made
intentionally.
E CASH output for DRAM bank 1
Can be configured as general purpose I/O port when CS1H
and DACK2 are not used.
External transfer request accept output pin for DMAC (ch. 2)
This function is available when transfer request output for
DMAC is enabled.
E WE output for DRAM bank 1 (“L” active)
Can be configured as general purpose I/O port when DW1 is
not used.
F Mode pins 0 to 2
MCU basic operation mode is set by these pins.
Directly connect these pins with VCC or VSS for use.
A Clock (oscillator) input
A Clock (oscillator) output
B External reset input
G NMI (non-maskable interrupt pin) input (“L” active)
(Continued)
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