MBM29F080A-90 View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MBM29F080A-90

FLASH MEMORY CMOS 8M (1M ×8) BIT

Fujitsu 

MBM29F080A-55/-70/-90

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Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of

time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations

and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will

be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase

Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)

See Figure 9 for the Data Polling timing specifications and diagrams.

DQ6

Toggle Bit I

The MBM29F080A also features the “Toggle Bit I” as a method to indicate to the host system that the embedded

algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or

Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive

attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four

write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth

WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of

the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.

In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 µs and then

stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for

the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about

100 µs and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause DQ6 to toggle.

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output disable functions as described in Table 2.

The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed

to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the

system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing

limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was

incorrectly used. If this occurs, reset the device.

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