MBM29F080A-55 View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MBM29F080A-55

FLASH MEMORY CMOS 8M (1M ×8) BIT

Fujitsu 

MBM29F080A-55/-70/-90

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RY/BY

Ready/Busy

The MBM29F080A provides a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with

either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase

operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands

with the exception of the Erase Suspend command. If the MBM29F080A is placed in an Erase Suspend mode,

the RY/BY output will be high, by means of connecting with a pull-up resistor to VCC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during RESET pulse. Refer to Figure 11 for a detailed timing diagram. The RY/BY pin is pulled

high in standby mode.

Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

RESET

Hardware Reset

The MBM29F080A device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL)

for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to

the read mode 20 µs after the RESET pin is driven low. If a hardware reset occurs during a program operation,

the data at that particular location will be indeterminate.

When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be

accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the

RESET pin is taken high, the device requires tRH of wake up time until outputs are valid for read access.

The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded

Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s

microprocessor to read the boot-up firmware from the Flash memory.

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