MC13109AFTA View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC13109AFTA Datasheet PDF : 28 Pages
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MC13109A
ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C)
Characteristic
Measure
Condition
Pin
Symbol
Min
Typ
Max
Unit
PLL PIN INTERFACE
EN to Clk Setup Time
–
Data to Clk Setup Time
–
Hold Time
–
Recovery Time
–
Input Pulse Width
–
Input Rise and Fall Time
–
EN, Clk
tsuEC
200
–
–
ns
Data, Clk
tsuDC
100
–
–
ns
Data, Clk
th
90
–
–
ns
EN, Clk
trec
90
–
–
ns
EN, Clk
tw
100
–
–
ns
Data
tr, tf
–
Clk
EN
–
9.0
µs
MPU Interface
90% of PLL Vref to
–
tpuMPU
–
100
–
µs
Power–Up Delay
Data, Clk, EN
PLL LOOP
2nd LO Frequency
–
LO2 In
fLO
–
LO2 Out
“Tx VCO” Input Frequency Vin = 200 mVpp
Tx VCO
ftxmax
–
–
12
MHz
–
80
MHz
PLL I/O Pin Specifications
The 2nd LO, Rx and Tx PLL’s and MPU serial interface are
normally powered by the internal voltage regulator at the “PLL
Vref” pin. The “PLL Vref” pin is the output of a voltage regulator
which is powered from the “VCC Audio” power supply pin.
Therefore, the maximum input and output levels for most PLL
I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the
regulated voltage at the “PLL Vref” pin. The ESD protection
diodes on these pins are also connected to “PLL Vref”.
Internal level shift buffers are provided for the pins (Data, Clk,
EN, Clk Out) which connect directly to the microprocessor.
The maximum input and output levels for these pins is VCC.
Figure 5 shows a simplified schematic of the PLL I/O pins.
Figure 5. PLL I/O Pin Simplified Schematics
PLL Vref
(2.2 V)
VCC Audio PLL Vref
(2.0 to 5.5 V) (2.2 V)
VCC Audio
(2.0 to 5.5 V)
I/O
In
1.0 kΩ
Out
LO2 In, LO2 Out,
Rx PD, Tx PD and
Tx VCO Pins
2.0 µA
Data, Clk, and EN Pins
Clk Out Pin
Microprocessor Serial Interface
The “Data”, “Clk”, and “EN” pins provide an MPU serial
interface for programming the reference counters, the
transmit and receive channel divider counter and various
control functions. The “Data” and “Clk” pins are used to load
data into the shift register. Figure 6 shows “Data” and “Clk”
pin timing. Data is clocked on positive clock transitions.
Figure 6. Data and Clock Timing Requirement
tr
tf
90%
Data,
10%
Clk, EN
50%
Data
tsuDC
th
50%
Clk
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–Bit address is loaded
into the shift register and latched into the 8–Bit address latch
register. Then, up to 16–Bits of data is loaded into the shift
register and latched into the data latch register specified by
the address that was previously loaded. Figure 7 shows the
timing required on the EN pin. Latching occurs on the
negative EN transition.
MOTOROLA RF/IF DEVICE DATA
15
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