MC13109A View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC13109A Datasheet PDF : 28 Pages
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MC13109A
“Clk Out” Divider Programming
MPU “Clk Out” Power–Up Default Divider Value
The “Clk Out” pin is derived from the 2nd local oscillator and
The power–up default divider value is “divide by 10”. This
can be used to drive a microprocessor, thereby reducing the
provides an MPU clock of about 1.0 MHz after initial
number of crystals required. Figure 19 shows the relationship
power–up. The reason for choosing this relatively low clock
between the crystal frequency and the clock output for
frequency after intial power–up is that some microprocessors
different divider values. Figure 20 shows the “Clk Out” register
that operate down to a 2.0 V power supply have a maximum
bit values.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 19. Clock Output Values
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Crystal
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Frequency
2
Clock Output Divider
3
5
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 10.24 MHz 5.120 MHz 3.413 MHz 2.048 MHz 1.024 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 11.15 MHz 5.575 MHz 3.717 MHz 2.230 MHz 1.115 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 12.00 MHz 6.000 MHz 4.000 MHz 2.400 MHz 1.200 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 20. Clock Output Divider
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Clk Out
Bit #1
Clk Out
Bit #2
Clk Out
Divider Value
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
0
2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
1
3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
0
5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
1
10
clock frequency of 1.0 MHz. After initial power–up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another is “smooth”
(i.e., there will be no narrow clock pulses to disturb the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13109A and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kΩ
resistor is included on–chip in–series with the “Clk Out” output
driver. A small capacitor can be connected to the “Clk Out” line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the “Clk Out” line.
Volume Control
The volume control can be programmed in 2.0 dB gain steps
from –14 dB to 16 dB. The power–up default value is 0 dB.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Volume Control
Bit #3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
Volume Control
Bit #2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Figure 21. Volume Control
Volume Control
Bit #1
Volume Control
Bit #0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Volume
Control #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Gain/Attenuation
Amount
–14 dB
–12 dB
–10 dB
– 8.0 dB
– 6.0 dB
– 4.0 dB
– 2.0 dB
0 dB
2.0 dB
4.0 dB
6.0 dB
8.0 dB
10 dB
12 dB
14 dB
16 dB
Gain Control Register
Figure 22. Gain Control Latch Bits
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 22 and 23.
MSB
5–Bit CD Threshold Control
LSB
20
MOTOROLA RF/IF DEVICE DATA
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