MC13109FB View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC13109FB Datasheet PDF : 28 Pages
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MC13109
“Clk Out” Divider Programming
MPU “Clk Out“ Power–Up Default Divider Value
The “Clk Out” pin is derived from the 2nd local oscillator
The power–up default divider value is “divide by 10”. This
and can be used to drive a microprocessor, thereby reducing
provides an MPU clock of about 1.0 MHz after initial
the number of crystals required. Figure 23 shows the
power–up. The reason for choosing this relatively low clock
relationship between the crystal frequency and the clock
frequency after intial power–up is that some microprocessors
output for different divider values. Figure 24 shows the “Clk
that operate down to a 2.0 V power supply have a maximum
Out” register bit values.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 23. Clock Output Values
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Crystal
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Frequency
2
Clock Output Divider
3
5
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 10.24 MHz 5.120 MHz 3.413 MHz 2.560 MHz 2.048 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 11.15 MHz 5.575 MHz 3.717 MHz 2.788 MHz 2.230 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 12.00 MHz 6.000 MHz 4.000 MHz 3.000 MHz 2.400 MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 24. Clock Output Divider
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Clk Out
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit #1
Clk Out
Bit #0
Clk Out
Divider Value
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
0
2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
1
3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
0
5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
1
10
clock frequency fo 1.0 MHz. After initial power–up, the MPU
can change the clock divider value to set the clock to the
desired operating frequency. Special care has been taken in
the design of the clock divider to ensure that the transition
between one clock divider value and another is “smooth”
(i.e., there will be no narrow clock pulses to disturb the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13109 and the
microprocessor has the potential to radiate noise which can
cause problems in the system especially if the clock is a
square wave digital signal with large high frequency
harmonics. In order to minimize radiated noise, a 1.0 kΩ
resistor is included on–chip in–series with the “Clk Out” output
driver. A small capacitor can be connected to the “Clk Out” line
on the PCB to form a single pole low pass filter. This filter will
significantly reduce noise radiated from the “Clk Out” line.
Volume Control
The volume control can be programmed in 2.0 dB gain
steps from –14 dB to +16 dB. The power–up default value is
0 dB.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁolumÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁBeit0000000011111111C#ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3ontÁÁÁÁÁÁÁrÁÁÁÁÁÁÁÁÁÁÁÁol ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVoÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁlumBÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁeit0000111100001111C#2ÁÁÁÁÁÁÁoÁÁÁÁÁÁÁÁÁÁÁÁntrÁÁÁÁÁÁÁÁÁÁÁÁÁÁoÁÁÁÁÁl ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVFoiÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁlguumBrÁÁÁÁÁÁÁeÁÁÁÁÁÁÁÁÁÁÁiÁet0011001100110011C#21o5ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁn.tVrooÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁllumÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁe CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁoVnotlÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁuromBleiÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁtÁ0101010101010101C#0oÁÁÁÁÁÁÁnÁÁÁÁÁÁÁÁÁÁÁÁtroÁÁÁÁÁÁÁÁÁÁÁÁÁÁlÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCVÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁoÁonl111111u0123456789t102345rmÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁoÁle#ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁGaÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁiÁnA/–––––––A24681111m86420111ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ....ÁÁÁÁt0246Á0000....420to0000deddddddddudddBnddddBBBBBBBBBBBnÁÁÁÁÁÁÁuÁÁÁÁÁÁÁÁÁÁÁBBBBÁtatioÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁn ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Gain Control Register
The gain control register contains bits which control the
Carrier Detect threshold. Operation of these latch bits are
explained in Figures 26 and 27.
Figure 26. Gain Control Latch Bits
MSB 5–Bit CD Threshold Control LSB
MOTOROLA ANALOG IC DEVICE DATA
21
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