MC13783JVK5 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC13783JVK5

Power Management and Audio Circuit

Freescale Semiconductor 

Functional Description

CS

CLK

Tselsu

Tclkper

Tclkhigh Tclklow

Tselhld Tsellow

Twrtsu

MOSI

Trden

MISO

Twrthld

Trdsu

Trdhld

Trddis

Figure 4. SPI Interface Timing Diagram

Table 6. SPI Interface Timing Specifications

Parameter

Description

T min (ns)

Tselsu

Time CS has to be high before the first rising edge of CLK

20

Tselhld

Time CS has to remain high after the last falling edge of CLK

20

Tsellow

Time CS has to remain low between two transfers

20

Tclkper

Clock period of CLK1

50

Tclkhigh

Part of the clock period where CLK has to remain high

20

Tclklow

Part of the clock period where CLK has to remain low

20

Twrtsu

Time MOSI has to be stable before the next rising edge of CLK

5

Twrthld

Time MOSI has to remain stable after the rising edge of CLK

5

Trdsu

Time MISO will be stable before the next rising edge of CLK

5

Trdhld

Time MISO will remain stable after the falling edge of CLK

5

Trden

Time MISO needs to become active after the rising edge of CS

5

Trddis

Time MISO needs to become inactive after the falling edge of CS

5

1 Equivalent to a maximum clock frequency of 20 MHz.

Table 7. SPI Interface Logic IO Specifications

Parameter

Condition

Min

Max

Units

Input High CS, MOSI, CLK

—

0.7*VCC VCC+0.5 V

Input Low CS, MOSI, CLK

—

0

0.3*VCC V

Output Low MISO, INT

Output sink 100 μA

0

0.2

V

Output High MISO, INT

Output source 100 μA VCC-0.2

VCC

V

Note: VCC refers to PRIVCC and SECVCC respectively.

MC13783 Technical Data, Rev. 3.5

20

Freescale Semiconductor

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