MC13110AFB View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MC13110AFB

Universal Cordless Telephone Subsystem IC

Motorola => Freescale 

MC13110A/B MC13111A/B

ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;

Test Circuit Figure 1.)

Characteristic

Figure

Input

Pin

Measure

Pin

Symbol Min

Typ

Max Unit

LOW BATTERY DETECT

Output Low Voltage (Vin = 1.0 V)

BATTERY DETECT INTERNAL THRESHOLD

After Electronic Adjustment of VB Voltage

BD Select = (111)

BD Select = (110)

BD Select = (101)

BD Select = (100)

BD Select = (011)

BD Select = (010)

BD Select = (001)

PLL PHASE DETECTOR

Output Source Current

(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)

Output Sink Current

(VPD = Gnd + 0.5 V to PLL Vref – 0.5 V)

PLL LOOP CHARACTERISTICS

Maximum 2nd LO Frequency

(No Crystal)

1

Ref1

BD1 Out

VOL

Ref2

BD2 Out

1, 128 VCC Audio BD2 Out

IBS7

IBS6

IBS5

IBS4

IBS3

IBS2

IBS1

–

–

Rx PD

IOH

Tx PD

–

–

Rx PD

IOL

Tx PD

–

LO2 In

–

f2ext

–

0.2

0.4

V

V

3.381 3.455 3.529

3.298 3.370 3.442

3.217 3.287 3.357

3.134 3.202 3.270

2.970 3.034 3.098

2.886 2.948 3.010

2.802 2.862 2.922

–

1.0

–

mA

–

1.0

–

mA

–

12

–

MHz

Maximum 2nd LO Frequency

–

(With Crystal)

Maximum Tx VCO (Input Frequency),

–

Vin = 200 mVpp

PLL VOLTAGE REGULATOR

Regulated Output Level (IL = 0 mA, after Vref

1

Adjustment)

–

LO2 In

f2ext

–

12

–

MHz

LO2 Out

–

Tx VCO ftxmax

–

80

–

MHz

–

PLL Vref

VO

2.4

2.5

2.6

V

Line Regulation (IL = 0 mA, VCC = 3.0 to 5.5 V)

Load Regulation (IL = 1.0 mA)

1

VCC Audio PLL Vref VRegLine

–

11.8

40

mV

1

VCC Audio PLL Vref VReg

–20

–1.4

–

mV

Load

MICROPROCESSOR SERIAL INTERFACE

Input Current Low (Vin = 0.3 V, Standby Mode)

1

–

Data,

IIL

–5.0

0.4

–

µA

Clk, EN

Input Current High (Vin = 3.3 V, Standby Mode)

1

–

Data,

IIH

–

1.6

5.0

µA

Clk, EN

Hysteresis Voltage

–

–

Data,

Vhys

–

1.0

–

V

Clk, EN

Maximum Clock Frequency

–

Data,

–

EN, Clk

–

–

2.0

–

MHz

Input Capacitance

–

Data,

–

Clk, EN

Cin

–

8.0

–

pF

EN to Clk Setup Time

106

Data to Clk Setup Time

105

Hold Time

105

Recovery Time

106

Input Pulse Width

–

MPU Interface Power–Up Delay (90% of PLL Vref 108

to Data,Clk, EN)

–

EN, Clk tsuEC

–

200

–

ns

–

Data, Clk tsuDC

–

100

–

ns

–

Data, Clk

th

–

90

–

ns

–

EN, Clk

trec

–

90

–

ns

–

EN, Clk

tw

–

100

–

ns

–

–

tpuMPU

–

100

–

µs

MOTOROLA ANALOG IC DEVICE DATA

9

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