NLV14517BDWR2G(2014) View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
NLV14517BDWR2G Datasheet PDF : 6 Pages
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MC14517B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.65 ns/pF) CL + 9.5 ns
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 390 ns
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns
tPLH, tPHL = (0.5 ns/pF) CL + 115 ns
Clock Pulse Width
Symbol
tTLH, tTHL
tPLH, tPHL
tWH
Typ
VDD
Min (Note 6) Max
Unit
5.0
−
10
−
15
−
ns
100
200
50
100
40
80
5.0
−
10
−
15
−
ns
475
770
210
300
140
215
5.0
330
170
−
ns
10
125
75
−
15
100
60
−
Clock Pulse Frequency
fcl
5.0
−
3.0
1.5
MHz
10
−
6.7
4.0
15
−
8.3
5.3
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
−
10
See (Note 7)
15
Data to Clock Setup Time
tsu
5.0
0
– 40
−
ns
10
10
– 15
−
15
15
0
−
Data to Clock Hold Time
th
5.0
150
75
−
ns
10
75
25
−
15
35
10
−
Write Enable to Clock Setup Time
tsu
5.0
400
170
−
ns
10
200
65
−
15
110
50
−
Write Enable to Clock Release Time
trel
5.0
380
160
−
ns
10
180
55
−
15
100
40
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
fo
C
D
(f = 1/2 fo)
REPETITIVE WAVEFORM
D
C
VDD
VSS
VDD
VSS
50 mF
VDD
D Q16 Q32 Q48 Q64
C
WE
D
C
WE
VSS
ID
Q16 Q32 Q48 Q64
CL CL CL CL
CL
CL
CL
CL
Figure 1. Power Dissipation Test Circuit and Waveform
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