MC33099 View Datasheet(PDF) - Motorola => Freescale
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MC33099 Datasheet PDF : 13 Pages
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MC33099
activated, activating all biasing into the normal state and
activating the start–up LRC mode. After engine cranking and
immediately after initial engine start up, the system battery
voltage is generally low while a WOT condition occurs. For
this case, the slow LRC response is in effect to prevent
excessive torque loading on the engine by the alternator
during engine start up. The Gate duty cycle at start–up with
WOT (DCstart) is the minimum LRC duty cycle and will
increase at the LRC rate. Once the system voltage returns to
voltage Vset, the normal LRC response will occur as
previously described.
Field Coil Drive and Device Protection
The external MOSFET provides PWM drive current from
the system battery to the field coil for system voltage
regulation. The gate–to–source voltage for this MOSFET is
provided by the IC’s Gate to Source terminal drive voltage.
During the ON state, the AND4 gate activates switch S3 to
couple the Gate drive pull–up source current (Ipu) to the Gate
output. Current Ipu drives the gate of the MOSFET to the
charge pump Gate voltage Vg (typically 23V), causing the
MOSFET to drive the field coil terminal to near the system
battery voltage. Voltage Vg has a minimum charge pump
Gate voltage (Vg(min)) of 21.5V. This high Gate to Source
voltage minimizes power dissipation in the external MOSFET
by minimizing a Drain To Source ON resistance (Rds(ON) of
the MOSFET during the ON state. This results in a typical
Lamp Drain ON voltage (Vd(sat)) of about 0.3V at a Lamp
Drain current of 400 mA as measured from the Lamp Drain
Pin to ground. During the OFF state, the AND4 gate activates
switch S3 to couple a Gate drive pull–down sink current (Ipd)
to the Gate output. Current Ipd pulls the Gate voltage to the
Source voltage, turning OFF the MOSFET and its associated
field coil current. The limited gate current drive of the
MOSFET Gate capacitance reduces the magnitude and
frequency of the high frequency components associated with
the Gate duty cycle waveform, minimizing RFI. Zener diode
Z1 is employed to provide a Gate–To–Source clamping
voltage (Vgs) which limits and protect the Gate–To–Source
voltage of the external MOSFET.
When the external MOSFET fails to increase the source
(or field coil terminal) voltage to within a source short circuit
threshold voltage (VTssc) of the Battery terminal voltage
(VTssc < [Vbat – Vsource]), a shorted–source comparator Css
outputs a short circuit signal to a Gate polling circuit. A
shorted field coil to ground is an example of this fault
condition. This Gate polling circuit provides short gate polling
pulses to the AND4 gate to allow the IC to test for an
unshorted condition without damaging the external MOSFET.
The polling duty cycle is 1.56%, (or about a 158 µS ON pulse)
at a frequency of fmsb/4, or 98.6 Hz. When the source
shorting condition is removed, comparator Css provides a
no–short signal to the gate polling circuitry which provides a
logic 1 to the AND4 gate which then operates normally.
The AND4 gate is also driven by the no load dump
(LD–bar) line from the Over Voltage Detector circuitry. Thus
during a load dump system over voltage condition, a logic 0 is
provided to the AND4 gate from the Over Voltage Detector
circuit and all Gate drive is terminated.
A flyback diode MR850 is externally provided to limit the
negative source voltage on the field terminal (and the Source
terminal) caused by a turn–OFF transition of the field current.
The forward current through this diode is approximately the
peak field current prior to field current turn OFF.
Fault Lamp Indicator – Drive and Protection
The fault indicator lamp is driven by an internal N–channel
MOSFET lamp driver which controls the lamp current. The
lamp is coupled between the ignition switch and the Lamp
Drain pin of the lamp driver. The Lamp Gate of the lamp
driver is driven by the lamp driver circuitry or from an external
Lamp Gate pin. Inputs to the lamp driver circuitry are from an
output of an AND2 gate, an output of a thermal limit circuit,
and an output of a current limit circuit. By applying an external
Lamp Gate override voltage (Vgo) to the Lamp Gate pin (5),
the Lamp Drain current will increase, providing lamp current
independent of the lamp driver logic state. When the lamp
driver circuity is forcing the lamp driver OFF, the Lamp Gate
pin resistance to ground will be about 4.6K ohms. The source
of the lamp driver is coupled to ground through an internal
current sense resistor Rs. When the lamp is ON, the Lamp
Drain ON voltage (Vd(sat)) is the Lamp Drain–to–ground
voltage measured at 400 mA of Lamp Drain current.
Normally, current flows through the lamp driver (and
lamp), indicating a fault when the output of the AND2 gate is
a logic 1. Assuming the lamp is not shorted, is not being
current limited, is not in the thermal shut down mode, and the
system is not in a load dump mode, the lamp ON current is
controlled by the output of the OR2 gate. The output of the
OR2 gate is a logic 1 and the lamp will normally be ON when
the UV (Under Voltage) line and the F2 output line are both a
logic 1 state, indicating an under voltage condition when
frequency fph > f2. The output of the OR2 gate is also a logic
1 when the output of the OV(Over Voltage) line is a logic 1,
indicating an over voltage condition, or the output of the F1
line is also a logic 1, indicating a loss of phase signal (fph <
f1) due to a broken phase wire, broken or slipping belt, or
otherwise failed alternator or open field circuit.
When the lamp current exceeds a lamp drain short circuit
current (Idsc), the voltage across resistor Rs will exceed a
current limit threshold voltage associated with the current
limit circuitry. As a result, a signal is sent to the lamp driver
circuitry to limit the lamp drive and regulates the lamp current
to current Idsc. When the power dissipation of the lamp driver
causes the temperature of the lamp driver to exceed a
thermal shut–down temperature limit (TLim), a temperature
sensing diode (Dtl) causes the thermal limit circuitry to send a
signal to the lamp driver circuitry to limit the lamp drive
current and reduce the power dissipation and resulting
device temperature. When the lamp driver is ON, but the
Lamp Drain terminal voltage is not below the Battery terminal
voltage Vbat by at least a lamp drain short circuit threshold
voltage (VTdsc) or ([Vbat – Vdrain] < VTdsc), comparator Cds
will output a lamp short circuit signal to the Drain Polling
circuit to indicate a lamp shorted condition. The Drain Polling
circuit provides a low duty cycle polling output to the input of
the AND2 gate to poll the lamp driver ON, continuously
testing for a lamp short without damaging the lamp driver.
The polling duty cycle is 1.56%, (or about a 158uS ON pulse)
at a frequency of fmsb/4, or 98.6Hz. After the lamp short has
been removed, the comparator Cds outputs a lamp
not–shorted signal to the Drain Polling circuitry which
provides a logic 1 to the AND2 gate which then operates
normally.
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