MC33099 View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
MC33099 Datasheet PDF : 13 Pages
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MC33099
Internal Clock Oscillator and 8 Bit Counter
An internal clock oscillator is provided having a typical
oscillation frequency (fosc) of 101 kHz. The output of the
oscillator is coupled to an 8–Bit counter which provides 8
counting bits to the logic and the four most significant
counting bits (MSB) to the LRC circuitry and to a Digital to
Analog Converter (DAC) waveform generator. The output
MSB frequency (fmsb) of the 8 bit divider is about 395 Hz
(fmsb = fosc/256), which determines the PWM frequency at
the Gate output. An external LRC Test pin is provided for
accelerating internal testing of the LRC function and logic.
Under normal operation the LRC Test pin is grounded by an
internal 10k ohm resistance to ground. Under accelerated
test conditions, the LRC Test pin voltage is 5.0 V, and a fourth
bit (fosc/16) from the 8–Bit divider is used to determine the
PWM Gate frequency. Thus, the rates are accelerated by a
factor of 16.
Low Pass Filter, DAC and Analog Duty Cycle Regulator
Comparator
The output voltage Vo of combiners CB1 and CB2 is
coupled to an input of a 300 Hz low pass filter (Rf,Cf) to
remove high frequency components of system noise at Vbat
and thus associated with voltages Vls, or Vrs. The output of
the low pass filter is coupled to a unity–gain buffer FB which
provides a filter buffer FB output.
The 4 MSBs of the 8–Bit counter causes the DAC to
generate a 4–Bit 395 Hz voltage waveform having 16
descending 1.75 mV steps, ramping from Vref to [Vref – 28
mV], where Vref is the 2.0 V reference voltage.
An analog duty cycle comparator (Cdc) compares the DAC
output voltage waveform to the voltage at the FB output (Vfb).
When voltage Vfb is less then voltage [Vref – 28 mV],
comparator Cdc outputs a logic 1, for a 100% duty cycle.
When voltage Vfb is greater than Vref, comparator Cdc
outputs a logic 0, for a 0% duty cycle. When (Vref – 28 mV] <
Vfb < Vref, comparator Cdc outputs a duty cycle defined by the
High/Low output voltage ratio for each period (about 2.54
mS) of the DAC output voltage waveform.
Basic System Voltage Regulation
From a system voltage regulation viewpoint, the voltages
Vrem and Vl from the Remote or Local connections
respectively are scaled to the Remote Sense and Local
Sense inputs as voltages Vrs and Vls respectively and
transferred to the FB output as voltage Vfb. Voltage Vfb is
compared to the DAC output voltage waveform to generate
the ON and OFF time of the analog duty cycle waveform.
When voltage Vfb is less than Vref – 28 mV, the output of
comparator Cdc is in a high state. This high state propagates
through an AND3 gate, an OR1 gate and an AND4 gate to
activate switch S3, generating a fully ON or High Gate drive
voltage. When voltage Vfb is greater than Vref, the output of
comparator Cdc is in a low state. This low state propagates
through the AND3 gate, the OR1 gate and the AND4 gate to
activate switch S3 to generate a fully OFF or low Gate drive
voltage. Assuming voltage Vref is 2.0V, and Vfb = Vrs, and the
local or remote input resistive scale factor of 7.45, the
external MOSFET provides a fully ON field current when the
system voltage is less than 7.45 (Vref – 28 mV) or 14.6V. The
field current is also fully OFF when the system voltage is
greater than 7.45 (Vref) or 14.9V. When voltage Vfb is less
than any portion of the DAC waveform voltage, comparator
Cdc output is high to produce an ON field current. When
voltage Vfb is greater than any portion of the DAC waveform
voltage, comparator Cdc output is low, to produce an OFF
field current. Thus the system feedback will regulate the
PWM duty cycle of the field current from 0 to 100% over
about a 210 mV system regulation voltage range (dVreg).
The system voltage is centered at 14.8V, where a 50% duty
cycle field current results for an average system load current,
and the duty cycle regulation frequency is (fosc/256), or 395
Hz. Since voltage Vref has a negative TC, voltage Vset will
also have a regulation voltage temperature coefficient
(TCVreg) of about –11 mV/°C.
Input Phase and Frequency Switch Response
The phase voltage Vph results from the alternator’s stator
AC output voltage being applied to the Phase input terminal.
A phase detection threshold voltage (VTph) is approximately
4.0V due to the 1.25V phase reference voltage for the phase
comparator (Cph), and the 3.22 voltage ratio associated with
the phase input resistor divider. The phase input resistance
(Rph) is typically 60k Ω. A Phase Filter pin (13) is coupled to
the input of Comparator Cph, providing for an external phase
filter capacitance, when filtering of high frequency phase
noise is desired. A typical value of .003uF to AGND provides
for an input phase 3db roll–off frequency of about 10kHz.
Comparator Cph also provides about 480 mV of hysteresis at
the Phase input pin. Comparator Cph further provides a
phase signal binary output voltage having a phase frequency
of fph and is applied to digital frequency switches F1 and F2.
Switch F1 outputs a logic 1 when frequency fph is less then
phase detection frequency f1. Frequency f1 is equal to
frequency fmsb/8, or 49.3 Hz for a 101 kHz oscillator
frequency. Switch F2 outputs a logic 1 when the frequency fph
is greater then the low/high transition frequency f2.
Frequency f2 is equal to frequency 3fmsb/4, or 296 Hz for a
101 kHz oscillator frequency. These frequency switches are
used to define the Load Response Control region of
operation, an undervoltage at a high RPM fault condition, and
a low RPM fault condition due to a broken or lose belt.
Load Response Control (LRC)
The LRC circuit consists of a digital duty cycle generator,
an analog/digital (A/D) duty cycle comparator and tracking
circuit, an up/down control switch, an up/down (U/D) counter,
a programmable divider (Np), and a multiplexer (MUX).
During normal operation, the LRC circuit becomes active and
generates digital duty cycle control of the Gate drive when
frequency fph is less than frequency f2 (f1 < fph < f2). The slow
LRC response becomes inactive and the analog duty cycle
controls the Gate drive when frequency fph is greater than
frequency f2 (f1 < fph < f2). During initial ignition and initial
engine start, the LRC response is in effect, independent of
frequency fph, until system voltage is regulating at voltage
Vset.
The digital duty cycle generator receives the 4 MSBs from
the 8–Bit counter as input and generates 11 discrete digital
duty cycles on 11 output lines. The frequency of each duty
cycle waveform is about 395 Hz (fmsb) which results from the
MSB of the 8–Bit division of the 101 kHz OSC clock
frequency. The minimum duty cycle on the 1st output line is
31.25% and the maximum duty cycle on the 11th output line
is 93.75%. The duty cycle difference between each
incremental duty cycle is 6.25%. All 11 duty cycle generator
output lines are coupled as data inputs to the MUX.
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