MC33099CDW/R2 View Datasheet(PDF) - Motorola => Freescale
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MC33099CDW/R2 Datasheet PDF : 18 Pages
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TYPICAL APPLICATIONS
When the phase frequency is greater than frequency
f2 (fph > f2), the N divide factor is reduced to 4. As a result,
the LRC circuitry still functions as previously described, but
the rate of digital duty cycle increase or decrease is a
maximum LRC rate (Rlrc(max) ) of about 10 ms/step. Thus a
step increase in the analog duty cycle from 31.25% to 100%
will cause about a 110 ms delay before the digital duty cycle
provides a 100% duty cycle at the output of the AND3 GATE
(and GATE drive).
The conditions for LRC response also occur during an
initial engine start up period after engine cranking even when
a WOT condition occurs (fph > f2). When the ignition switch is
turned ON, comparator Cign is activated, activating all biasing
into the normal state and activating the start-up LRC mode.
After engine cranking and immediately after initial engine
start up, the system BATTERY voltage is generally low while
a WOT condition occurs. For this case, the slow LRC
response is in effect to prevent excessive torque loading on
the engine by the alternator during engine start up. The
GATE duty cycle at start-up with WOT (DCstart) is the
minimum LRC duty cycle and will increase at the LRC rate.
Once the system voltage returns to voltage Vset, the normal
LRC response will occur as previously described.
FIELD COIL DRIVE AND DEVICE PROTECTION
The external MOSFET provides PWM drive current from
the system BATTERY to the field coil for system voltage
regulation. The GATE-to-Source voltage for this MOSFET is
provided by the IC's GATE-to-SOURCE pin drive voltage.
During the ON state, the AND4 GATE activates switch S3 to
couple the GATE drive pull-up source current (Ipu) to the
GATE output. Current Ipu drives the GATE of the MOSFET to
the charge pump GATE voltage Vg (typically 23 V), causing
the MOSFET to drive the field coil pin to near the system
BATTERY voltage. Voltage Vg has a minimum charge pump
GATE voltage (Vg(min)) of 21.5 V. This high GATE-to-Source
voltage minimizes power dissipation in the external MOSFET
by minimizing a Drain-to-Source ON resistance (RDS(ON)) of
the MOSFET during the ON state. This results in a typical
Lamp Drain ON voltage (Vd(sat)) of about 0.3 V at a Lamp
Drain current of 400 mA as measured from the LAMP DRAIN
pin to ground. During the OFF state, the AND4 GATE
activates switch S3 to couple a GATE drive pull-down sink
current (Ipd) to the GATE output. Current Ipd pulls the GATE
voltage to the Source voltage, turning OFF the MOSFET and
its associated field coil current. The limited GATE current
drive of the MOSFET GATE capacitance reduces the
magnitude and frequency of the high-frequency components
associated with the GATE duty cycle waveform, minimizing
RFI. Zener diode Z1 is employed to provide a GATE-to-
Source clamping voltage (Vgs), which limits and protects the
GATE-to-Source voltage of the external MOSFET.
When the external MOSFET fails to increase the source
(or field coil pin) voltage to within a source short circuit
threshold voltage (VTssc) of the BATTERY pin voltage
(VTssc < [Vbat - Vsource] ), a shorted-source comparator Css
outputs a short circuit signal to a GATE polling circuit. A
shorted field coil to ground is an example of this fault
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condition. This GATE polling circuit provides short GATE
polling pulses to the AND4 GATE to allow the IC to test for an
unshorted condition without damaging the external MOSFET.
The polling duty cycle is 1.56%, or about a 158 µs ON pulse
at a frequency of fmsb /4, or 98.6 Hz. When the source
shorting condition is removed, comparator Css provides a no-
short signal to the GATE polling circuitry, which provides a
logic [1] to the AND4 GATE, which then operates normally.
The AND4 GATE is also driven by the no load dump (LD)
line from the Overvoltage Detector circuitry. Thus during a
load dump system overvoltage condition, a logic [0] is
provided to the AND4 GATE from the Overvoltage Detector
circuit and all GATE drive is terminated.
A flyback diode MR850 is externally provided to limit the
negative source voltage on the field pin (and the SOURCE
pin) caused by a turn-OFF transition of the field current. The
forward current through this diode is approximately the peak
field current prior to field current turn OFF.
FAULT LAMP INDICATOR — DRIVE AND
PROTECTION
The fault indicator lamp is driven by an internal N-channel
MOSFET lamp driver, which controls the lamp current. The
lamp is coupled between the ignition switch and the LAMP
DRAIN pin of the lamp driver. The Lamp GATE of the lamp
driver is driven by the lamp driver circuitry or from an external
LAMP GATE pin. Inputs to the lamp driver circuitry are from
an output of an AND2 GATE, an output of a thermal limit
circuit, and an output of a current limit circuit. By applying an
external Lamp GATE override voltage (Vgo) to the LAMP
GATE pin (5), the Lamp Drain current will increase, providing
lamp current independent of the lamp driver logic state. When
the lamp driver circuity is forcing the lamp driver OFF, the
LAMP GATE pin resistance to ground will be about 4.6 kΩ.
The source of the lamp driver is coupled to ground through an
internal current sense resistor RS. When the lamp is ON, the
Lamp Drain ON voltage (Vd(sat)) is the Lamp Drain-to-ground
voltage measured at 400 mA of Lamp Drain current.
Normally, current flows through the lamp driver (and
lamp), indicating a fault when the output of the AND2 GATE
is a logic [1]. Assuming the lamp is not shorted, is not being
current limited, is not in the thermal shut down mode, and the
system is not in a load dump mode, the lamp ON current is
controlled by the output of the OR2 GATE. The output of the
OR2 GATE is a logic [1] and the lamp will normally be ON
when the UV (undervoltage) line and the F2 output line are
both a logic [1] state, indicating an undervoltage condition
when frequency fph > f2. The output of the OR2 GATE is also
a logic [1] when the output of the OV (overvoltage) line is a
logic [1], indicating an overvoltage condition, or the output of
the F1 line is also a logic [1], indicating a loss of phase signal
(fph < f1) due to a broken phase wire, broken or slipping belt,
or otherwise failed alternator or open field circuit.
When the lamp current exceeds a lamp drain short circuit
current (Idsc), the voltage across resistor Rs will exceed a
current limit threshold voltage associated with the current
limit circuitry. As a result, a signal is sent to the lamp driver
Analog Integrated Circuit Device Data
Freescale Semiconductor
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