33285_07 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

33285_07

Dual High-Side TMOS Driver

Freescale Semiconductor 

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

INTRODUCTION

The 33285 contains only one charge pump for two

outputs.The outputs, OUT1 and OUT2, are switched ON and

OFF by the input (IN) .There are three ways to control the

outputs:

OUT1 can be switched alone

OUT1 and OUT2 can be switched together

OUT2 can be switched when OUT1 is already on

In the last case, the voltage drop on OUT1 when charging

OUT2 is limited.

The external capacitor (CCP) connected to the CHARGE

PUMP (CP) pin is used to store the charge continuously

delivered by the charge pump. The voltage on this pin is

limited to a maximum value VCPMAX. Both outputs are

sourced with a constant current from CCP to switch them ON.

Additionally, the gates of the power FETs are precharged

from voltage power supply (VCC) to prevent CCP from being

discharged by a voltage on OUT1 or OUT2, is still lower than

VVCC. The values of the output voltages are limited to

VOUT1MAX and VOUT2MAX.

The power FET on OUT1 is protected against an

exceeded gate-source voltage by an internal zener diode.

Channel One protects the N-Channel power FET on OUT1

undercurrent and short-circuit conditions. The drain-source

voltage of the FET on OUT1 is checked if Channel One is

switched ON. The internal error voltage threshold determines

the maximum drain-source voltage allowing the power FET to

stay in the ON state. If the measured drain-source voltage

exceeds the internal error voltage threshold, the output of the

short-circuit protection comparator (SCPC) is enabled. If the

output of the SCPC is active longer than tOCDET, output

OUT1 is switched OFF.

After switching OFF the power FET on OUT1 by an short-

circuit condition, the power FET can only be turned ON again

by the input IN.

When switching OFF the power FETs their gate capacities

are discharged by a constant current, IOUTOFF.

If the input IN is disconnected, the 33285 outputs, OUT1

and OUT2, are in the OFF state.

If overvoltage occurs on the DRAIN (DRN) pin for a time

period longer than tLDDET, OUT2 is switched ON for the time

tOUT2ACT. In an overvoltage condition OUT1 is OFF if IN is

below VIH.

INTERNAL ZENER DIODE

An on-chip zener diode is placed between OUT1 and The

SOURCE (SRC). Design guarantees VZ > VTH1. Zener

clamping voltage between OUT1 and SRC is VTH1 < VZ <

20 V

PWM CAPABILITY

The CPIC2 is PWM capable on OUT2. The loss of charge

ON CCP when switching ON OUT2 is refreshed until the Start

on the next PWM cycle to a value sufficient to guarantee the

specified turn ON behavior.

The PWM capability is measured with a test circuit and

load conditions:

• PWM cycle is period T = 20 ms ; OUT2 is switched ON

from 10 to 90 percent of T

• Test condition VIN ramps 2.5 V ≤ 5.0 V according to PWM

cycle defined above

CROSS TALK BETWEEN OUT1 AND OUT2

If output OUT2 is switched ON while OUT1 is already ON,

the voltage drop occurring on OUT1 is limited.

Voltage drop on OUT1:

• 10 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V

• 7.0 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V

Each time OUT1 is switched ON, a current ILCDET is

sourced out of the SRC pin for the time tLCDET to check if

there is an external leakage current on that node in the

application. The high-side switch on OUT1 is turned ON only

if the test is successful.

33285

8

Analog Integrated Circuit Device Data

Freescale Semiconductor

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