MC33298(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC33298
(Rev.:2006)

Eight Output Switch with Serial Peripheral Interface I/O

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

.

Table 7. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING

Output Rise Time (VPWR = 13 V, RL = 26 Ω) (29)

Output Fall Time (VPWR = 13 V, RL = 26 Ω) (29)

Output Turn ON Delay Time (VPWR = 13 V, RL = 26 Ω) (30)

Output Turn-OFF Delay Time (VPWR = 13 V, RL = 26 Ω) (31)

Output Short Fault Disable Report Delay (32)

SFPD = 0.2 x VDD

Output OFF Fault Report Delay (33)

SFPD = 0.2 x VDD

tR

0.4

1.5

20

µs

tF

0.4

2.5

20

µs

tDLY(ON)

1.0

5.0

15

µs

tDLY(OFF)

1.0

5.0

15

µs

tDLY(SF)

25

µs

50

100

tDLY(OFF)

25

µs

50

100

DIGITAL INTERFACE TIMING

SCLK Clock Period (34)

tpSCLK

500

—

—

ns

SCLK Clock High Time

twSCLKH

175

—

—

ns

SCLK Clock Low Time

Required Low State Duration for Reset (VIL < 0.2 VDD) (35)

twSCLKL

175

—

tw(RST)

250

50

—

ns

—

ns

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

tLEAD

250

50

—

ns

Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)

tLAG

250

50

—

ns

SI to Falling Edge of SCLK (Required for Setup Time)

tSISU

125

25

—

ns

Falling Edge of SCLK to SI (Required for Hold Time)

tSI(HOLD)

125

25

—

ns

SO Rise Time (CL = 200 pF)

trSO

—

25

75

ns

SO Fall Time (CL = 200 pF)

SI, CS, SCLK, Incoming Signal Rise Time (36)

SI, CS, SCLK, Incoming Signal Fall Time (36)

Time from Falling Edge of CS to SO Low Impedance (37)

Time from Rising Edge of CS to SO High Impedance (38)

tfSO

—

trSI

—

tfSI

—

tSO(EN)

—

tSO(DIS)

—

25

75

ns

—

200

ns

—

200

ns

—

200

ns

—

200

ns

Notes

29. Output Rise and Fall time respectively measured across a 26 Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.

30. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26 Ω

resistive load.

31. Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26 Ω

resistive load.

32. Output Short Fault Delay time measured from rising edge of CS to IOUT -= 2.0 A point with output ON, VOUT = 5.0 V, and SFPD = 0.2

x VDD. See Figures 8 and 10.

33. Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9.

34. Clock period include 75 ns rise plus 75 ns fall transition in addition to clock high and low time.

35. RST Low duration measured with outputs enabled and going to OFF or disabled condition.

36. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

37. Time required for output status data to be available for use at the SO pin.

38. Time required for output status data to be terminated at the SO pin.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33298

9

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