MC33874BPNA/R2 View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

Manufacturer

MC33874BPNA/R2

Quad High Side Switch (Quad 35mΩ)

ROHM Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)

Over-current High Detection Blanking Time

CS to CSNS Valid Time(24)

Watchdog Timeout(25)

WD[1:0] : 00

WD[1:0] : 01

WD[1:0] : 10

WD[1:0] : 11

Direct Input Switching Frequency (DICR D3 = 0)

SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)

tOCH

1.0

5.0

20

μs

t CNSVAL

–

–

10

μs

ms

t WDTO0

t WDTO1

t WDTO2

t WDTO3

446

223

1800

900

558

279

2250

1125

725

363

2925

1463

fPWM

-

300

-

Hz

Maximum Frequency of SPI Operation

Required Low-state Duration for RST(26)

Rising Edge of CS to Falling Edge of CS (Required Setup Time)(27)

Rising Edge of RST to Falling Edge of CS (Required Setup Time)(27)

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(27)

Required High-state Duration of SCLK (Required Setup Time)(27)

Required Low-state Duration of SCLK (Required Setup Time)(27)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(27)

SI to Falling Edge of SCLK (Required Setup Time)(28)

Falling Edge of SCLK to SI (Required Setup Time)(28)

SO Rise Time

CL = 200pF

SO Fall Time

CL = 200pF

SI, CS, SCLK, Incoming Signal Rise Time(28)

SI, CS, SCLK, Incoming Signal Fall Time(28)

Time from Falling Edge of CS to SO Low-impedance(29)

Time from Rising Edge of CS to SO High-impedance(30)

Time from Rising Edge of SCLK to SO Data Valid(31)

0.2 VDD ≤ SO ≤ 0.8 x VDD, CL = 200pF

f SPI

–

t WRST

–

t CS

–

t ENBL

–

t LEAD

–

t WSCLKh

–

t WSCLKl

–

t LAG

–

t SI (SU)

–

t SI (HOLD)

–

t RSO

–

t FSO

–

t RSI

–

t FSI

–

t SO(EN)

–

t SO(DIS)

–

t VALID

–

–

3.0

MHz

50

350

ns

–

300

ns

–

5.0

μs

50

167

ns

–

167

ns

–

167

ns

50

167

ns

25

83

ns

25

83

ns

ns

25

50

ns

25

50

–

50

ns

–

50

ns

–

145

ns

65

145

ns

ns

65

105

Notes

24. Time necessary for the CSNS to be with ±5% of the targeted value.

25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output

driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured

watchdog timeouts.

26. RST low duration measured with outputs enabled and going to OFF or disabled condition.

27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller.

28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

29. Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on CS.

30. Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on CS.

31. Time required to obtain valid data out from SO following the rise of SCLK.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33874

11

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