MC34065−H, L
Vref
1
5
1
3
2
4
R2
5
R1
R
Bias
R
20k
5.0Vref
+
+−
_
Osc.
1.0mA
+
−
EA1
VClamp
−
2R
+
1.0V
R
ǒ Ǔ VClamp ≈
1.67
R2
R1
)
1
+ 0.33 x 10−3 (R1)
VCC
16
+
−+
_
PWM
Latch 1
S
Q
R
Ipk(max) ≈ VClamp
RS
Where: 0 ≤ VClamp ≤ 1.0 V
Vin
Q1
7
6
RS
Vref
15
1
R
Bias
R
20k
3
Osc.
2
1.0mA
4
1.0M
+
−
EA1
2R
1.0V
R
5
C
tSoft−Start ≈ 2100 C in μF
Figure 19. Adjustable Reduction of Clamp Level
VCC
Vin
16
Figure 20. Soft−Start Circuit
VCC
Vin
16
Vref
15
R
+
5.0Vref
−+
Bias
R
_
+
1
20k
+−
+
5.0Vref
−+
_
+
+−
3
_
Osc
2
PWM
Latch 1
4
+
VClamp
−
S
Q
−
2R
+
R
EA1
1.0V
R
Q1
7
−
PWM
Latch 1
S
−
Q
+
R
Rg
Q1
7
D1
1N5819
C
R2
5
Where: 0 ≤ VClamp ≤ 1.0 V
R1
MPSA63
Ipk(max) ≈ VClamp
RS
6
RS
6
RS
Series gate resistor Rg may be needed to damp high frequency parasitic
ǒ Ǔ VClamp ≈
1.67
R2 ) 1
R1
tSoft−Start = In
1
VC
1 − 3 VClamp
C
R1R2
R1 ) R2
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate−source circuit. Rg will decrease the MOSFET
switching speed. Schottky diode D1 is required if circuit ringing drives the
output pin below ground.
Figure 21. Adjustable Reduction of Clamp Level
with Soft−Start
VCC
Vin
16
+
5.0Vref
_
+
_
+
_
+
_
PWM
Latch 1
S
−
Q
+
R
Control Circuitry Ground
to Pin 8
D SENSEFET
G
S Power Ground to
Input Source Return
7
MK
Drive Ground
to Pin 9
VPin 6 ≈
RS Ipk rDS(on)
rDM(on) + RS
6 RS
1/4W
If: SENSEFET = MTP10N10M
RS = 200
Then: VPin 6 = 0.075 Ipk
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a reduction
of the Ipk(max) clamp level must be implemented. Refer to Figures 19 and 21.
Figure 23. Current Sensing Power MOSFET
Figure 22. MOSFET Parasitic Oscillations
VCC
16
+
5.0Vref
_+
_
+
_
+
_
PWM
Latch 1
S
−
Q
+
R
Vin
Q1
7
R
6
C
RS
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 24. Current Waveform Spike Suppression
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