56F8122 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
56F8122 Datasheet PDF : 136 Pages
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56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 21 GPIO lines
• 48-pin LQFP Package
6 PWM Outputs
Fault Inputs
PWMA or
SPI1 or
GPIOA
RESET
4
VCAP VDD
2
4
VSS
4
VDDA VSSA
Program Controller
and Hardware
Looping Unit
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
3
AD0
3
AD1
3
VREF
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
XDB2
XAB1
XAB2
TEMP_SENSE
4K x 16 Boot
Flash
PAB
PDB
4
Quadrature
Decoder 0 or
Quad
Data Memory
4K x 16 Flash
4K x 16 RAM
CDBR
CDBW
Timer A or
GPIO B
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Quad Timer C
2
or SCI0
or GPIOC Decoding
Peripheral
Device Selects
RW
Control
IPWDB IPRDB
2
FlexCAN or Peripherals
GPIOC
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Interrupt
Watchdog Controller
IRQA
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
*Includes On-Chip
Relaxation Oscillator
56F8322/56F8122 Block Diagram
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
3
Preliminary
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