56F8002 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8002 Datasheet PDF : 100 Pages
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Signal/Connection Descriptions
3.4 Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002.
Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature
Distribution Centers, or online at http://www.freescale.com.
Table 2. 56F8006/56F8002 Device Documentation
Topic
Description
DSP56800E Reference
Manual
Detailed description of the 56800E family architecture,
16-bit digital signal controller core processor, and the
instruction set
56F800x Peripheral
Reference Manual
Detailed description of peripherals of the 56F8006 and
56F8002 devices
56F80x Serial Bootloader Detailed description of the Serial Bootloader in the
User Guide
56F800x family of devices
56F8006/56F8002 Electrical and timing specifications, pin descriptions, and
Technical Data Sheet package descriptions (this document)
56F8006/56F8002 Errata Details any chip issues that might be present
Order Number
DSP56800ERM
MC56F8006RM
TBD
MC56F8006
MC56F8006E
4 Signal/Connection Descriptions
4.1 Introduction
The input and output signals of the 56F8006/56F8002 are organized into functional groups, as detailed in Table 3. Table 4
summarizes all device pins. In Table 4, each table row describes the signal or signals present on a pin, sorted by pin number.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins Number of Pins Number of Pins
in 28 SOIC
in 32 LQFP
in 48 LQFP
Power Inputs (VDD, VDDA)
2
2
4
Ground (VSS, VSSA)
Reset1
3
3
4
1
1
1
Pulse Width Modulator (PWM) Ports1
10
12
12
Serial Peripheral Interface (SPI) Ports1
5
7
7
Serial Communications Interface 0 (SCI) Ports1
4
5
5
Inter-Integrated Circuit Interface (I2C) Ports1
6
7
7
Analog-to-Digital Converter (ADC) Inputs1
16
18
24
High Speed Analog Comparator Inputs1
13
15
25
Programmable Gain Amplifiers (PGA)1
4
4
4
Dual Timer Module (TMR) Ports1
8
10
10
Programmable Delay Block (PDB)1
—
—
1
Clock1
5
5
5
JTAG/Enhanced On-Chip Emulation (EOnCE1)
4
4
4
1 Pins may be shared with other peripherals. See Table 4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Freescale Semiconductor
11
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