56F8002 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
56F8002 Datasheet PDF : 100 Pages
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Overview
3.3 Architecture Block Diagram
The 56F8006/56F8002’s architecture is shown in Figure 2 and Figure 3. Figure 2 illustrates how the 56800E system buses
communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core.
Figure 3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module
(SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other
peripherals.
DSP56800E Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Address
Generation
Unit
(AGU)
M01
N3
ALU1
ALU2
R0
R1
R2
R3
R4
R5
N
SP
XAB1
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Program
Memory
Data/
Program
RAM
Bit-
Manipulation
Unit
Enhanced
OnCE™
JTAG TAP
A2
A1
B2
B1
C2
C1
D2
D1
Y
Y1
Y0
X0
A0
B0
C0
D0
Data
Arithmetic
Logic Unit
(ALU)
MAC and ALU Multi-Bit Shifter
Figure 2. 56800E Core Block Diagram
IPBus
Interface
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Freescale Semiconductor
9
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