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MC56F8037VLH View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
Manufacturer
MC56F8037VLH
Freescale
Freescale Semiconductor Freescale
MC56F8037VLH Datasheet PDF : 181 Pages
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connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar
manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for
additional information.
The PWM_reload_sync output can be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s
Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to
SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used
to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel
independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1.
56F8037/56F8027 Data Sheet, Rev. 6
10
Freescale Semiconductor

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