To/From IPBus Bridge
CLKGEN
(OSC/PLL)
Timer A
Interrupt
Controller
Low Voltage Interrupt
POR and LVI
4
Quadrature Decoder 0
4
Timer D
Timer B
4
Quadrature Decoder 1
SPI1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
System POR
RESET
SIM
COP Reset
COP
FlexCAN
2
2
FlexCAN2
PWMA
PWMB
13
SYNC Output
13
SYNC Output
ch3i
ch2i
Timer C
2
ch3i
ch2i
GPIOF
4
SPI0
2
SCI0
2
SCI1
ADCB
8
ADCA
8
TEMP_SENSE
1
IPBus
NOT available on the 56F8165 device.
Note: ADC A and ADC B use the same voltage
reference circuit with VREFH, VREFP, VREFMID,
VREFN, and VREFLO pins.
Figure 1-2 Peripheral Subsystem
56F8365 Technical Data, Rev. 7
12
Freescale Semiconductor
Preliminary