M5206EAN View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

M5206EAN

ColdFire® Microprocessor

Freescale Semiconductor 

Freescale Semiconductor, Inc.

MCF5206e Overview

1.1.4 Internal SRAM

The 8-Kbyte on-chip SRAM provides one clock-cycle access for the ColdFire core. The SRAM can store

processor stack and critical code or data segments to maximize performance.

1.1.5 DRAM Controller

The MCF5206e DRAM controller provides a glueless interface for up to 2 banks of DRAM, each of which

can range from 128 Kbytes to 256 Mbytes. The controller supports an 8-, 16-, or 32-bit data bus. A unique

addressing schemes allows for increases in system memory size without rerouting address lines and

rewiring boards. The controller operates in fast page or regular mode and supports extended-data-out (EDO)

DRAMs.

1.1.6 MAC Module

The MAC unit provides high performance digital signal processing capabilities for the MCF5206e.

Integrated as an execution unit in the processor’s operand execution pipeline, the MAC unit implements a

three-stage arithmetic pipeline with sustained instruction issue rate of one MAC cycle for 16x16 operations

(while also supporting 32x32 operations). The MAC opcodes provide a full feature set of extensions to the

standard ColdFire instruction set for signed and unsigned operands. In addition to executing the

MAC-specific instructions, this unit also performs all integer multiply opcodes, providing higher

performance for this class of operation.

1.1.7 DMA Controller

The MCF5206e provides two fully programmable DMA channels for quick data transfer (32 bits, with

packing and unpacking supported). Each channel has an external request pin associated with it. Single and

dual address mode is supported with the ability for program bursting and cycle stealing. With

auto-alignment enabled, efficient block transfers of up to 128 bits can be achieved.

1.1.8 Dual UART Modules

The UART modules contain independent receivers and transmitters that are clocked by the UART internal

timer. This timer is clocked by the system clock or an external clock supplied by the TIN pin. Data formats

can be 5, 6, 7 or 8 bits with even, odd, or no parity, and as many as two stop bits in 1/16 increments.

Four-byte receive buffers and 2-byte transmit buffers minimize CPU service calls. The UART modules also

provide several error-detection and maskable-interrupt capabilities. Modem support includes

request-to-send (RTS) and clear-to-send (CTS) signals.

The system clock provides the clocking function via a programmable prescaler. Select full duplex, autoecho

loopback, local loopback, and remote loopback modes. The programmable UARTs can interrupt the CPU

on various normal or error condition events.

1.1.9 Dual Timer Module

The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer

for use in any of the three modes. One mode captures the timer value with an external event; another mode

triggers an external signal or interrupts the CPU when the timer reaches a set value, while a third mode

counts external events. The timer unit has an 8-bit prescaler that allows programming of the clock input

MOTOROLA

MCF5206e Integrated ColdFire® Microprocessor Product Brief

5

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