MCF5253 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MCF5253 Datasheet PDF : 32 Pages
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Signal Description
Table 3. MCF5253 Signal Index (continued)
Signal Name
Mnemonic
Function
Input/
Output
QSPI data out
RCK/QSPIDIN/QSPIDOUT/GPIO26
QSPIDOUT/SFSY/GPIO27
QSPI data out
In/Out
QSPI chip selects
QSPICS0/EBUIN4/GPIO15
QSPICS1/EBUOUT2/GPIO16
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
QSPI chip selects
In/Out
System oscillator in
CRIN
System input
In
System oscillator out CROUT
System output
Out
Reset In
RSTI
Processor reset input
In
Freescale Test Mode TEST[2:0]
TEST pins.
In
Linear regulator output LINOUT
Output of 1.2 V to supply core
Out
Linear regulator input LININ
Input, typically I/O supply (3.3V)
In
Linear regulator ground LINGND
High Impedance
HI_Z
Assertion tri-states output signal pins In
Debug Data
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Display of captured processor data
DDATA1/RTS1/SDATA2_BS2/GPIO2 and break-point statuses
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
In/Out
Processor Status
PST0/GPIO50
PST1/GPIO49
PST2/INTMON2/GPIO48
PST3/INTMON1/GPIO47
Indication of internal processor
status.
In/Out
Processor clock
PSTCLK/GPIO51
Processor clock output
Out
Test Clock
TCK
Clock signal for IEEE 1149.1A JTAG In
Test Reset/
Development Serial
Clock
DSCLK/TRST
Multiplexed signal that is
In
asynchronous reset for JTAG
controller. Also, clock input for debug
module.
Test Mode Select/Break TMS/BKPT
Point
Multiplexed signal that is test mode
In
select in JTAG mode and a hardware
break-point in debug mode
Test Data Input/
Development Serial
Input
TDI/DSI
Multiplexed serial input for the JTAG
In
or background debug module.
Test Data
Output/Development
Serial Output
TDO/DSO
Multiplexed serial output for the
Out
JTAG or background debug module
Reset
State
–
–
–
–
–
–
–
–
–
Hi-Z
Hi-Z
–
–
–
–
–
–
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 2
10
Freescale Semiconductor
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