MCM20027IBBL View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

MCM20027IBBL

Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control, timing, and pixel correction features

Motorola => Freescale 

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

ImageMOS

7.0 Analog Signal Processing Chain Overview

The MCM20027’s analog signal processing (ASP)

chain incorporates Correlated Double Sampling (CDS),

Frame Rate Clamp (FRC), two Digitally Programmable

Gain Amplifiers (DPGA), Offset Correction (DOVA), and

a 10-bit Analog to Digital Converter (ADC).

To see a pictorial depiction of this chain refer to “Speci-

fications” on page 2

7.1 Correlated Double Sampling (CDS)

The uncertainty associated with the reset action of a ca-

pacitive node results in a reset noise which is equal to

kTC; C being the capacitance of the node, T the temper-

ature and k the Boltzmann constant. A common way of

eliminating this noise source in all image sensors is to

use Correlated Double Sampling. The output signal is

sampled twice, once for its reset (reference) level and

once for the actual video signal. These values are sam-

pled and held while a difference amplifier subtracts the

reference level from the signal output. Double sampling

of the signal eliminates correlated noise sources (see

.“Conceptual block diagram of CDS implementation.”

on page 15)

AVIN

CDSP1

S/H1

CDSP2

S/H2

V+

AMP

V-

Figure 12. Conceptual block diagram of CDS

implementation.

7.2 Frame Rate Clamp (FRC)

The FRC (Figure 13) is designed to provide a feed for-

ward dark level subtract reference level measurement.

In the automatic FRC mode, the optical black level ref-

erence is re-established each time the image sensor

begins a new frame. The MCM20027 uses optical black

(dark) pixels to aid in establishing this reference.

LRCLMP

Previous

LRCLMP

1X

Stage

LRCLMP

1X

LRCLMP

CapLRCA

0.1µf

-

BUF

+

Vcm

+

BUF

-

CapLRCB

0.1µf

FRC

+

Diff

A- mp

CLRCA

Vcm

LRCLMP

V+

V-

LRCLMP

Vcm

CLRCB

Figure 13. FRC Conceptual Block Diagram

On the MCM20027, dark pixel input signals should be

sampled for a minimum of 137µs to allow the two 0.1µF

capacitors at the CLRCA and CLRCB pins sufficient

time to charge for 10-bit accuracy. This guarantees that

the FRC’s “droop” will be maintained at <750 µV, thus

assuring the specified ADC 10-bit accuracy at +0.5

LSB. Therefore, at maximum operational frequency

(13.5 MHz), the imager would require a number of

frames to establish the dark pixel reference for subse-

quent active pixel processing. The dark pixel sample

period is automatically controlled internally and it is set

to skip the first 3 dark rows and then sample the next 2

dark rows. When “dark clamping” is active, each dark

pixel is processed and held to establish pixel reference

level at the CLRCA and CLRCB pins. During this period,

the FRC’s differential outputs (V+ and V- on the Diff

Amp, Figure 13) are clamped to Vcm. Together, these

actions help to eliminate the dark level offset, simulta-

neously establishing the desired zero code at the ADC

output.

Care should be exercised in choosing the capacitors for

the CLRCA, B to reflect different frame rates.

The user can disable this function via the FRC Definition

Register; Table 56 on page 63 and the Power

Configuration Register, Table 21, on page 41

which will allow the ASP chain to drift in offset Per-Column

Digital Offset Voltage Adjust (DOVA), and controls the

number of rows to clamp on.

Revision 8.4 - 24 Oct 2002 : MCM20027

MOTOROLA

15

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