MCM36F8DG10 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MCM36F8DG10 Datasheet PDF : 11 Pages
| |||
PIN DESCRIPTIONS
Pin Locations
3, 4, 5, 6, 7, 8, 17, 18, 19, 20,
21, 22, 27, 28, 29, 30, 31, 32
82
39, 40, 103, 104
73, 74, 141, 142
(a) 49, 50, 53, 54, 55, 56, 57, 58,
(b) 63, 64, 65, 66, 69, 70, 71, 72
(c) 109, 110, 111, 112, 125, 126, 129, 130
(d) 131, 132, 133, 134, 135, 136, 139, 140
41, 105
42, 106
46, 45, 122, 121
35, 36
81
9, 10, 25, 26, 51, 52,
61, 62, 85, 86, 93,
94, 107, 108, 137, 138
1, 2, 15, 16, 33, 34, 37, 38, 43, 44, 47, 48,
59, 60, 67, 68, 79, 80, 101, 102, 119, 120,
123, 124, 127, 128, 143, 144
11, 12, 13, 14, 23, 24,
75, 76, 77, 78, 83, 84,
87, 88, 89, 90, 91, 92, 95,
96, 97, 98, 99, 100, 113,
114, 115, 116, 117, 118
Symbol
A0 – A17
ADSP
BW0 – BW3
DP0 – DP3
DQ0 – DQ31
E0, E1
G0, G1
K0 – K3
PD0, PD1
WE
VDD
VSS
NC
Type
Input
Input
Input
I/O
Description
Synchronous Address Inputs: These inputs are registered and
must meet setup and hold times.
Synchronous Addresss Status Controller: Initiates read, write, or
chip deselect cycle.
Synchronous Byte Write Inputs: x refers to the byte being written
(byte a, b, c, d). WE overrides BWx.
Synchronous Parity Data Inputs/Outputs.
Synchronous Data Inputs/Outputs.
Input
Input
Input
Output
Input
Supply
Synchronous Chip Enable: Active low to enable chip. Negated
high — deselects chip when ADSP is asserted.
Asynchronous Output Enable Input.
Clock: This signal registers the address, data in, and all control
signals except G.
Presence Detect Bits.
Synchronous Global Write: This signal writes all bytes
regardless of the status of the BWx signals. If only byte write
signals SBx are being used, tie this pin high.
Power Supply: 3.3 V + 10%, – 5%.
Supply Ground.
— No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM36F8•MCM36F9
5
Share Link: 