MCM67D709FN20 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MCM67D709FN20 Datasheet PDF : 12 Pages
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STREAM CYCLE (See Note 1)
Processor Frequency
60 MHz
MCM67D709–16
50 MHz
MCM67D709–20
Parameter
Symbol
Min
Max
Min
Max Unit Notes
Stream Cycle Time
tKHKH
16
—
20
—
ns 1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
ns
Stream Access Time
tKHQV
—
6
—
7
ns
Setup Times:
A
tAVKL
2
—
2
—
ns
W tWHKH
2
2
PIE tPIEVKH
2
2
SIE tSIEVKH
2
2
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP tDVKH
2
2
Hold Times:
A
tKLAX
2
—
2
—
ns
W tKHWX
2
2
PIE tKHPIEX
2
2
SIE tKHSIEX
2
2
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP tKHDX
2
2
Output Enable High to Q High–Z
tPOEHQZ
0
6
0
8
ns
3
tSOEHQZ
Output Enable Low to Q Active
tPOELQX
0
—
0
—
ns
3
tSOELQX
Output Enable Low to Output Valid
tPOELQV
—
5
—
6
ns
tSOELQV
NOTES:
1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus.
2. All stream cycle timing is referenced from K.
3. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX, tSOEHQZ is less than tSOELQX, for a given device.
MCM67D709
8
MOTOROLA FAST SRAM
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