MCM72F8 View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
MCM72F8 Datasheet PDF : 12 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM72F8–8
MCM72F9–8
MCM72F8–9
MCM72F9–9
Parameter
Symbol
Min
Max
Min
Max
Cycle Time
tKHKH
10
—
11
—
Clock Access Time
tKHQV
—
8
—
9
Output Enable to Output Valid
tGLQV
—
3.5
—
3.5
Clock High to Output Active
tKHQX1
0
—
0
—
Clock High to Output Change
tKHQX2
2
—
2
—
Output Enable to Output Active
tGLQX
0
—
0
—
Output Disable to Q High–Z
tGHQZ
—
3.5
—
3.5
Clock High to Q High–Z
tKHQZ
2
3.5
2
3.5
Clock High Pulse Width
tKHKL
4
—
4.5
—
Clock Low Pulse Width
tKLKH
4
—
4.5
—
Setup Times:
Address tAVKH
2
—
2
—
ADSP tADKH
Data In tDVKH
Write tWVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
ADSP, ADSC, ADV tKHADX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. In setup and hold times, write refers to either any SBx and SW or SGW is low.
2. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
MCM72F8–12
MCM72F9–12
Min
Max
16.6
—
—
12
—
5
0
—
2
—
0
—
—
3.5
2
3.5
5
—
5
—
2
—
0.5
—
Unit Notes
ns
ns
ns
ns 4, 5
ns
4
ns 4, 5
ns 4, 5
ns 4, 5
ns
ns
ns
ns
OUTPUT
Z0 = 50 Ω
TIMING LIMITS
RL = 50 Ω
VL = 1.25 V
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad-
dress setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.
Figure 2. AC Test Load
MCM72F8•MCM72F9
8
MOTOROLA FAST SRAM
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