MICRF010 View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
MICRF010 Datasheet PDF : 14 Pages
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Micrel
MICRF010
The Demodulator Filter Bandwidth
There is no external control to set the demodulator
bandwidth. The maximum bandwidth is 2000 hertz at 315
MHz. Maximum bandwidth scales linearly with operating
frequency. To minimize data pulse stretching, one must
calculate the “demodulator BW required” to be certain that
it does not exceed demodulator filter bandwidth of
MICRF010 at operating frequency. For “demodulator BW
required” calculation, one needs to identify the shortest
pulse within the data profile and use equation 8 below:
Demodulator BW Required =
0.65
(8)
shortest pulse - width
Refer to the “Electrical Characteristics” for the exact filter
bandwidth at a chosen frequency.
Power Supply Bypass Capacitors
Supply bypass capacitors are strongly recommended. One
example is to use 0.1uF ceramic capacitor in parallel with
100pF ceramic capacitor for VDD.
Data Squelching
During quiet periods (no signal), the data output (DO pin)
transitions randomly with noise. Most decoders can
discriminate between this random noise and actual data.
For some systems, random transition due to noise during
quiet period is a problem. There are three possible
approaches to reduce this output noise:
1. Analog squelch to raise the demodulator threshold.
2. Digital squelch to disable the output when data is not
present.
3. Output filter to filter the (high frequency) noise
glitches on the data output pin.
The simplest solution is to perform analog squelch by
inducing a small offset, or squelch voltage, on the CTH pin
so that noise does not trigger the internal comparator,
Usually 20mV to 30mV on CTH pin is sufficient. This may
be achieved by connecting a several-meg-ohm resistor
from the CTH pin to either VSSBB or VDDBB, depending
upon the desired offset polarity. Since MICRF010’s
receiver AGC noise at the internal comparator input is
always the same (set by the AGC), the squelch-offset
requirement does not change as the local noise strength
changes from installation to installation. Introducing
squelch will reduce sensitivity and range. One should
introduce minimal offset to sufficiently quiet the output.
Typical squelch resistor values range from 10MΩ to 6.8MΩ
for low to high squelch strength.
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF010
are diagrammed in Figures 2 through 8. The ESD
protection diodes at all input and output pins are not
shown.
CTH Pin
VDD
Dem odul at or
Signal
PHI2B
PHI1B
TG2
TG1
CTH
~1.6V
VSS PHI2 VSS PHI1
Figure 2. CTH Pin
Figure 2 illustrates the CTH pin interface circuit. The CTH
pin is driven from a N-Channel MOSFET source-follower
with approximately 10µA of bias. Internal control signals
PHI1/PHI2 are related in a manner such that the
impedance across the transmission gates looks like a
“resistance” of approximately 150kΩ. The DC potential at
the CTH pin is approximately 1.6V
CAGC Pin
VDD
7uA
Compa-
rat or
16uA
CAGC
Timeout
85uA
160uA
VSS
Figure 3. CAGC Pin
Figure 3 illustrates the CAGC pin interface circuit. The
AGC control voltage is developed as an integrated current
into a capacitor CAGC. The attack current is nominally
1.5µA, while the decay current is a 10 times scaling of this,
approximately 15µA. Signal gain of the RF/IF strip inside
the IC diminishes as the voltage on CAGC decreases. By
simply adding a capacitor to CAGC pin, the attack/decay
time constant ratio is fixed at 10:1. Modification of the
attack/decay ratio is possible by adding resistance from the
CAGC pin to either VDDBB or VSSBB, as desired.
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across CAGC, and
improves recovery time in duty-cycled applications. To
further improve duty-cycle recovery, both push and pull
currents are increased by 45 times for approximately 10ms
after release of the SHUT pin. This allows rapid recovery of
any voltage droop on CAGC while in shutdown.
June 2005
9
M9999-063005
(408) 955-1690
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