MK2049-02 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
MK2049-02 Datasheet PDF : 12 Pages
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MK2049-02/03
Communications Clock PLLs
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (Note 1)
Minimum
Supply Voltage, VDD
Referenced to GND
Inputs and Clock Outputs
-0.5
Ambient Operating Temperature
MK2049-0xS
0
MK2049-0xSI
-40
Soldering Temperature
Max of 10 seconds
Storage Temperature
-65
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
4.75
Input High Voltage, VIH
2
Input Low Voltage, VIL
Input High Voltage, VIH
Pin 19 only
VDD-0.5
Input Low Voltage, VIL
Pin 19 only
Output High Voltage
IOH=-4 mA
VDD-0.4
Output High Voltage
IOH=-8 mA
2.4
Output Low Voltage
IOL=8 mA
Operating Supply Current, IDD
No Load, VDD=5.0V
Short Circuit Current
Each output
Input Capacitance, FS3:0
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency, External Mode
ICLK
Input Clock Pulse Width
10
Propagation Delay
ICLK to CLK2
Output-Output Skew, Zero Delay Selections
CLK1 to CLK2, Note 2
Output Clock Rise Time
0.8 to 2.0 V
Output Clock Fall Time
2.0 to 0.8 V
Output Clock Duty Cycle, High Time
At VDD/2
40
Actual mean frequency error versus target
Any clock selection
Typical
5
20
±100
7
8.000
0
0
Maximum
7
VDD+0.5
70
85
250
150
5.25
0.8
0.5
0.4
2
500
1.5
1.5
60
0
Units
V
V
°C
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
pF
kHz
ns
ns
ps
ns
ns
%
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CLK1 in the MK2049-02 may have the rising or falling edge aligned with the rising edge of CLK2. See the INPUT AND
OUTPUT SYNCHRONIZATION section for more details.
MDS 2049-02/03 B
3
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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