ML2240 View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
ML2240 Datasheet PDF : 24 Pages
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OKI Semiconductor
FEDL2240DIGEST-02
ML2240 Family
PIN DESCRIPTIONS
80-pin Plastic TQFP
Pin
1-3, 5, 66-68,
73-80
6
7
8-20, 22-24,
28-30, 32-35
25
27
36
37
38
39
41-44
Symbol
RD14-RD0
RD15/A-1
BYTE
RA22-RA0
XT
XT
RESET
WR
RD
CS
D3/STA3
D2/STA2
D1/STA1
D0/STA0
Type
I
I/O
I
O
I
O
I
I
I
I
I/O
Description
Data pins to connect an external memory.
Data is input when the ROE pin is at "L" level. Input data from outside
is not accepted when the ROE pin is at "H" level. The RD14-RD8 pins
do not accept input data from outside when the BYTE pin is at "L"
level.
Data pin of the externally connected memory when BYTE pin is at “H”
level.
The data is input when the ROE pin output is at "L" level. When the
ROE pin output is at "H" level, input data from outside is not accepted.
This pin becomes an address A-1 output pin when the device is in byte
mode. The address is output when the RCS pin is at "L" level. When
the RCS pin is at "H" level, this pin is in a high impedance state.
Word/byte switching pin of the externally connected memory.
When BYTE pin = “L” level: Byte mode
When BYTE pin = “H” level: Word mode
Address pins of an externally connected memory.
When RCS pin = “H”: High impedance
Wired to a crystal or ceramic oscillator.
Contains a feedback resistor of around 1 MΩ between this XT pin and
XT pin (pin 27).
When using an external clock, input the clock from this pin.
Wired to a crystal or ceramic oscillator.
When using an external clock, keep this pin open.
When “L” level is input to this pin, the device is reset to the initial state.
The oscillation stops, and AOUT output goes into “GND” level.
CPU interface write signal.
When CS pin is at “H” level, the WR signal cannot be input to the
device.
CPU interface read signal.
For parallel input interface, a status signal for each channel is output
from the D0-D7 pins when the RD pin is at "L" level. For the serial
input interface, a status signal for each channel is output from the
D5/D0 pin. This pin has a pull-up resistor built-in.
CPU interface chip select pin.
When CS pin is at “H” level, the WR, and RD signals cannot be input to
the device.
CPU interface data bus pins in the parallel input interface become
data input pins when WR is at “L” level.
They become channel status output pins in the serial input interface.
These pins also become channel status output pins when RD is at “L”
level.
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