ML2002(2008) View Datasheet(PDF) - Minilogic Device Corporation Limited

Part Name

Description

Manufacturer

ML2002
(Rev.:2008)

Static/Half Duty LCD COG Driver

Minilogic Device Corporation Limited 

ML2002 Preliminary

™ Pin Description

SYMBOL

BRES

LGND

INT

LVDD

MS

DIN

DCLK

LAI

LAO

PAD

I

-

I

-

I

I

I

I/O

O

CEI

I

CEO

O

DOUT

O

CNT

I

Q15

O

FIN

I

4,2,1Hz

O

256/125 Hz

O

125/62 Hz

O

LCLK

I

SEG1 .. SEG48

O

COM1A / B

O

PVDD

-

1/2 PVDD

I

1/2 Duty

I

CEN1A , CEN1B

I

T0

I

OOUT

O

COEN

I

IOEN

I

HPVDDEN

I

BEN

I

BCLK

I

OSC+ / -

I

SYNC

I/O

TFI

I

SYEN

I

TOUT

O

DUM1,2,3

-

DESCRIPTION

External reset input (active LOW)

Logic Ground

Alarm interrupt output

Logic Supply voltage

Input “0”, for slave mode

Data line input

Data clock input

It is an input pin which LOAD the display onto the LCD screen during rising edge.

Send out LOAD signal to the cascade slave ML2002 for displaying data onto LCD

screen.

Enable Chip for receive data/command in the DIN pin

Send out chip enable signal to the following cascade slave IC

Data output from the display data RAM

Input clock, count number of rising edge clock

Output High on the 16th clock from CNT

32768Hz Oscillator input

4, 2, 1Hz clock output

125Hz clock output for static/ 250 clock output for 1/2 duty

62Hz clock output for static/125 clock output for 1/2 duty

LCD Clock signal frequency

Segment output

Common output

Power VDD supply

1/2 PVDD LCD driving voltage

“1” – Halfduty, “0” – Static

Common Enable. “0” – Enable, “1” – Disable

Test mode. “0” – Normal mode, “1” – Testing Mode

32K internal clock output

Crystal oscillator enable. “0” – Enable, “1” – Disable

32K internal clock enable. “0” – Enable, “1” – Disable

1/2 PVDD enable. “0” – Enable, “1” – Disable

Blink control circuit enable “0” – Enable, “1” – Disable

Blink clock input

Crystal oscillator input

To synchronize COMMON signal to the following cascade IC

Master mode 2/4 pin interface, “1” - 2pin , “0” - 4pin

SYNC enable. SYEN is “1” – SYNC output, “0” – SYNC will be high impredence.

When select 4pin interface, it would output timer data.

Dummy Pad, Left it open only

Note : 1. In cascade format of ML2002(ie. ML2002-2U and –3U), one pin is the input of current ML2002

and the other is for the connection with the corresponding input pin of next ML2002.

2. Condition : FIN = 32 KHz Clock.

P11/13

Preliminary, November 2008

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